📄 prev_cmp_bahe.tan.qmsg
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "player2 register count:cnt\|lpm_counter:p2_rtl_1\|dffs\[4\] register count:cnt\|lpm_counter:p2_rtl_1\|dffs\[4\] 76.92 MHz 13.0 ns Internal " "Info: Clock \"player2\" has Internal fmax of 76.92 MHz between source register \"count:cnt\|lpm_counter:p2_rtl_1\|dffs\[4\]\" and destination register \"count:cnt\|lpm_counter:p2_rtl_1\|dffs\[4\]\" (period= 13.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.000 ns + Longest register register " "Info: + Longest register to register delay is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count:cnt\|lpm_counter:p2_rtl_1\|dffs\[4\] 1 REG LC17 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC17; Fanout = 7; REG Node = 'count:cnt\|lpm_counter:p2_rtl_1\|dffs\[4\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { count:cnt|lpm_counter:p2_rtl_1|dffs[4] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "d:/altera/71/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.000 ns) 8.000 ns count:cnt\|lpm_counter:p2_rtl_1\|dffs\[4\] 2 REG LC17 7 " "Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.000 ns; Loc. = LC17; Fanout = 7; REG Node = 'count:cnt\|lpm_counter:p2_rtl_1\|dffs\[4\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { count:cnt|lpm_counter:p2_rtl_1|dffs[4] count:cnt|lpm_counter:p2_rtl_1|dffs[4] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "d:/altera/71/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns ( 100.00 % ) " "Info: Total cell delay = 8.000 ns ( 100.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { count:cnt|lpm_counter:p2_rtl_1|dffs[4] count:cnt|lpm_counter:p2_rtl_1|dffs[4] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.000 ns" { count:cnt|lpm_counter:p2_rtl_1|dffs[4] count:cnt|lpm_counter:p2_rtl_1|dffs[4] } { 0.000ns 0.000ns } { 0.000ns 8.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "player2 destination 10.000 ns + Shortest register " "Info: + Shortest clock path from clock \"player2\" to destination register is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns player2 1 CLK PIN_4 5 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_4; Fanout = 5; CLK Node = 'player2'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { player2 } "NODE_NAME" } } { "bahe.vhd" "" { Text "D:/VHDL+拔河游戏机/bahe/bahe.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns count:cnt\|lpm_counter:p2_rtl_1\|dffs\[4\] 2 REG LC17 7 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC17; Fanout = 7; REG Node = 'count:cnt\|lpm_counter:p2_rtl_1\|dffs\[4\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { player2 count:cnt|lpm_counter:p2_rtl_1|dffs[4] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "d:/altera/71/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns ( 80.00 % ) " "Info: Total cell delay = 8.000 ns ( 80.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 20.00 % ) " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { player2 count:cnt|lpm_counter:p2_rtl_1|dffs[4] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.000 ns" { player2 player2~out count:cnt|lpm_counter:p2_rtl_1|dffs[4] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "player2 source 10.000 ns - Longest register " "Info: - Longest clock path from clock \"player2\" to source register is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns player2 1 CLK PIN_4 5 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_4; Fanout = 5; CLK Node = 'player2'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { player2 } "NODE_NAME" } } { "bahe.vhd" "" { Text "D:/VHDL+拔河游戏机/bahe/bahe.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns count:cnt\|lpm_counter:p2_rtl_1\|dffs\[4\] 2 REG LC17 7 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC17; Fanout = 7; REG Node = 'count:cnt\|lpm_counter:p2_rtl_1\|dffs\[4\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { player2 count:cnt|lpm_counter:p2_rtl_1|dffs[4] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "d:/altera/71/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns ( 80.00 % ) " "Info: Total cell delay = 8.000 ns ( 80.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 20.00 % ) " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { player2 count:cnt|lpm_counter:p2_rtl_1|dffs[4] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.000 ns" { player2 player2~out count:cnt|lpm_counter:p2_rtl_1|dffs[4] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { player2 count:cnt|lpm_counter:p2_rtl_1|dffs[4] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.000 ns" { player2 player2~out count:cnt|lpm_counter:p2_rtl_1|dffs[4] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { player2 count:cnt|lpm_counter:p2_rtl_1|dffs[4] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.000 ns" { player2 player2~out count:cnt|lpm_counter:p2_rtl_1|dffs[4] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" { } { { "lpm_counter.tdf" "" { Text "d:/altera/71/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" { } { { "lpm_counter.tdf" "" { Text "d:/altera/71/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { count:cnt|lpm_counter:p2_rtl_1|dffs[4] count:cnt|lpm_counter:p2_rtl_1|dffs[4] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.000 ns" { count:cnt|lpm_counter:p2_rtl_1|dffs[4] count:cnt|lpm_counter:p2_rtl_1|dffs[4] } { 0.000ns 0.000ns } { 0.000ns 8.000ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { player2 count:cnt|lpm_counter:p2_rtl_1|dffs[4] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.000 ns" { player2 player2~out count:cnt|lpm_counter:p2_rtl_1|dffs[4] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { player2 count:cnt|lpm_counter:p2_rtl_1|dffs[4] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.000 ns" { player2 player2~out count:cnt|lpm_counter:p2_rtl_1|dffs[4] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk_in 12 " "Warning: Circuit may not operate. Detected 12 non-operational path(s) clocked by clock \"clk_in\" with clock skew larger than data delay. See Compilation Report for details." { } { } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "cmp:com\|tmp_sta cmp:com\|tmp_record1\[1\] clk_in 4.0 ns " "Info: Found hold time violation between source pin or register \"cmp:com\|tmp_sta\" and destination pin or register \"cmp:com\|tmp_record1\[1\]\" for clock \"clk_in\" (Hold time is 4.0 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "9.000 ns + Largest " "Info: + Largest clock skew is 9.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in destination 21.000 ns + Longest register " "Info: + Longest clock path from clock \"clk_in\" to destination register is 21.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk_in 1 CLK PIN_83 55 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 55; CLK Node = 'clk_in'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_in } "NODE_NAME" } } { "bahe.vhd" "" { Text "D:/VHDL+拔河游戏机/bahe/bahe.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns division:div\|clk2 2 REG LC50 14 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC50; Fanout = 14; REG Node = 'division:div\|clk2'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.000 ns" { clk_in division:div|clk2 } "NODE_NAME" } } { "division.vhd" "" { Text "D:/VHDL+拔河游戏机/bahe/division.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 13.000 ns division:div\|clk3 3 REG LC1 15 " "Info: 3: + IC(2.000 ns) + CELL(7.000 ns) = 13.000 ns; Loc. = LC1; Fanout = 15; REG Node = 'division:div\|clk3'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "9.000 ns" { division:div|clk2 division:div|clk3 } "NODE_NAME" } } { "division.vhd" "" { Text "D:/VHDL+拔河游戏机/bahe/division.vhd" 32 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 21.000 ns cmp:com\|tmp_record1\[1\] 4 REG LC107 8 " "Info: 4: + IC(2.000 ns) + CELL(6.000 ns) = 21.000 ns; Loc. = LC107; Fanout = 8; REG Node = 'cmp:com\|tmp_record1\[1\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { division:div|clk3 cmp:com|tmp_record1[1] } "NODE_NAME" } } { "cmp.vhd" "" { Text "D:/VHDL+拔河游戏机/bahe/cmp.vhd" 63 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "17.000 ns ( 80.95 % ) " "Info: Total cell delay = 17.000 ns ( 80.95 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns ( 19.05 % ) " "Info: Total interconnect delay = 4.000 ns ( 19.05 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "21.000 ns" { clk_in division:div|clk2 division:div|clk3 cmp:com|tmp_record1[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "21.000 ns" { clk_in clk_in~out division:div|clk2 division:div|clk3 cmp:com|tmp_record1[1] } { 0.000ns 0.000ns 0.000ns 2.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 7.000ns 6.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in source 12.000 ns - Shortest register " "Info: - Shortest clock path from clock \"clk_in\" to source register is 12.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk_in 1 CLK PIN_83 55 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 55; CLK Node = 'clk_in'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_in } "NODE_NAME" } } { "bahe.vhd" "" { Text "D:/VHDL+拔河游戏机/bahe/bahe.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns division:div\|clk2 2 REG LC50 14 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC50; Fanout = 14; REG Node = 'division:div\|clk2'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.000 ns" { clk_in division:div|clk2 } "NODE_NAME" } } { "division.vhd" "" { Text "D:/VHDL+拔河游戏机/bahe/division.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 12.000 ns cmp:com\|tmp_sta 3 REG LC106 25 " "Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 12.000 ns; Loc. = LC106; Fanout = 25; REG Node = 'cmp:com\|tmp_sta'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { division:div|clk2 cmp:com|tmp_sta } "NODE_NAME" } } { "cmp.vhd" "" { Text "D:/VHDL+拔河游戏机/bahe/cmp.vhd" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.000 ns ( 83.33 % ) " "Info: Total cell delay = 10.000 ns ( 83.33 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 16.67 % ) " "Info: Total interconnect delay = 2.000 ns ( 16.67 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "12.000 ns" { clk_in division:div|clk2 cmp:com|tmp_sta } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "12.000 ns" { clk_in clk_in~out division:div|clk2 cmp:com|tmp_sta } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "21.000 ns" { clk_in division:div|clk2 division:div|clk3 cmp:com|tmp_record1[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "21.000 ns" { clk_in clk_in~out division:div|clk2 division:div|clk3 cmp:com|tmp_record1[1] } { 0.000ns 0.000ns 0.000ns 2.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 7.000ns 6.000ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "12.000 ns" { clk_in division:div|clk2 cmp:com|tmp_sta } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "12.000 ns" { clk_in clk_in~out division:div|clk2 cmp:com|tmp_sta } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns - " "Info: - Micro clock to output delay of source is 1.000 ns" { } { { "cmp.vhd" "" { Text "D:/VHDL+拔河游戏机/bahe/cmp.vhd" 34 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.000 ns - Shortest register register " "Info: - Shortest register to register delay is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cmp:com\|tmp_sta 1 REG LC106 25 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC106; Fanout = 25; REG Node = 'cmp:com\|tmp_sta'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { cmp:com|tmp_sta } "NODE_NAME" } } { "cmp.vhd" "" { Text "D:/VHDL+拔河游戏机/bahe/cmp.vhd" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns cmp:com\|tmp_record1\[1\] 2 REG LC107 8 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC107; Fanout = 8; REG Node = 'cmp:com\|tmp_record1\[1\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { cmp:com|tmp_sta cmp:com|tmp_record1[1] } "NODE_NAME" } } { "cmp.vhd" "" { Text "D:/VHDL+拔河游戏机/bahe/cmp.vhd" 63 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.000 ns ( 75.00 % ) " "Info: Total cell delay = 6.000 ns ( 75.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 25.00 % ) " "Info: Total interconnect delay = 2.000 ns ( 25.00 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { cmp:com|tmp_sta cmp:com|tmp_record1[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.000 ns" { cmp:com|tmp_sta cmp:com|tmp_record1[1] } { 0.000ns 2.000ns } { 0.000ns 6.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "4.000 ns + " "Info: + Micro hold delay of destination is 4.000 ns" { } { { "cmp.vhd" "" { Text "D:/VHDL+拔河游戏机/bahe/cmp.vhd" 63 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "21.000 ns" { clk_in division:div|clk2 division:div|clk3 cmp:com|tmp_record1[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "21.000 ns" { clk_in clk_in~out division:div|clk2 division:div|clk3 cmp:com|tmp_record1[1] } { 0.000ns 0.000ns 0.000ns 2.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 7.000ns 6.000ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "12.000 ns" { clk_in division:div|clk2 cmp:com|tmp_sta } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "12.000 ns" { clk_in clk_in~out division:div|clk2 cmp:com|tmp_sta } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { cmp:com|tmp_sta cmp:com|tmp_record1[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.000 ns" { cmp:com|tmp_sta cmp:com|tmp_record1[1] } { 0.000ns 2.000ns } { 0.000ns 6.000ns } "" } } } 0 0 "Found hold time violation between source pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0}
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