📄 prev_cmp_bahe.tan.qmsg
字号:
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "4 " "Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "music:mu\|pulse:u2\|pat1 " "Info: Detected ripple clock \"music:mu\|pulse:u2\|pat1\" as buffer" { } { { "pulse.vhd" "" { Text "D:/VHDL+拔河游戏机/bahe/pulse.vhd" 13 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "music:mu\|pulse:u2\|pat1" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "division:div\|clk3 " "Info: Detected ripple clock \"division:div\|clk3\" as buffer" { } { { "division.vhd" "" { Text "D:/VHDL+拔河游戏机/bahe/division.vhd" 32 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "division:div\|clk3" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "division:div\|clk4 " "Info: Detected ripple clock \"division:div\|clk4\" as buffer" { } { { "division.vhd" "" { Text "D:/VHDL+拔河游戏机/bahe/division.vhd" 43 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "division:div\|clk4" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "division:div\|clk2 " "Info: Detected ripple clock \"division:div\|clk2\" as buffer" { } { { "division.vhd" "" { Text "D:/VHDL+拔河游戏机/bahe/division.vhd" 21 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "division:div\|clk2" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} } { } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk_in register music:mu\|table:u1\|lpm_counter:counter_rtl_2\|dffs\[0\] register music:mu\|pulse:u2\|p_1\[3\] 21.28 MHz 47.0 ns Internal " "Info: Clock \"clk_in\" has Internal fmax of 21.28 MHz between source register \"music:mu\|table:u1\|lpm_counter:counter_rtl_2\|dffs\[0\]\" and destination register \"music:mu\|pulse:u2\|p_1\[3\]\" (period= 47.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "24.000 ns + Longest register register " "Info: + Longest register to register delay is 24.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns music:mu\|table:u1\|lpm_counter:counter_rtl_2\|dffs\[0\] 1 REG LC85 34 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC85; Fanout = 34; REG Node = 'music:mu\|table:u1\|lpm_counter:counter_rtl_2\|dffs\[0\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { music:mu|table:u1|lpm_counter:counter_rtl_2|dffs[0] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "d:/altera/71/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(8.000 ns) 10.000 ns music:mu\|pulse:u2\|p_1~4013 2 COMB SEXP95 1 " "Info: 2: + IC(2.000 ns) + CELL(8.000 ns) = 10.000 ns; Loc. = SEXP95; Fanout = 1; COMB Node = 'music:mu\|pulse:u2\|p_1~4013'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { music:mu|table:u1|lpm_counter:counter_rtl_2|dffs[0] music:mu|pulse:u2|p_1~4013 } "NODE_NAME" } } { "pulse.vhd" "" { Text "D:/VHDL+拔河游戏机/bahe/pulse.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.000 ns) 18.000 ns music:mu\|pulse:u2\|p_1~4019sexp5 3 COMB SEXP83 1 " "Info: 3: + IC(0.000 ns) + CELL(8.000 ns) = 18.000 ns; Loc. = SEXP83; Fanout = 1; COMB Node = 'music:mu\|pulse:u2\|p_1~4019sexp5'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { music:mu|pulse:u2|p_1~4013 music:mu|pulse:u2|p_1~4019sexp5 } "NODE_NAME" } } { "pulse.vhd" "" { Text "D:/VHDL+拔河游戏机/bahe/pulse.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.000 ns) 24.000 ns music:mu\|pulse:u2\|p_1\[3\] 4 REG LC94 32 " "Info: 4: + IC(0.000 ns) + CELL(6.000 ns) = 24.000 ns; Loc. = LC94; Fanout = 32; REG Node = 'music:mu\|pulse:u2\|p_1\[3\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { music:mu|pulse:u2|p_1~4019sexp5 music:mu|pulse:u2|p_1[3] } "NODE_NAME" } } { "pulse.vhd" "" { Text "D:/VHDL+拔河游戏机/bahe/pulse.vhd" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "22.000 ns ( 91.67 % ) " "Info: Total cell delay = 22.000 ns ( 91.67 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 8.33 % ) " "Info: Total interconnect delay = 2.000 ns ( 8.33 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "24.000 ns" { music:mu|table:u1|lpm_counter:counter_rtl_2|dffs[0] music:mu|pulse:u2|p_1~4013 music:mu|pulse:u2|p_1~4019sexp5 music:mu|pulse:u2|p_1[3] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "24.000 ns" { music:mu|table:u1|lpm_counter:counter_rtl_2|dffs[0] music:mu|pulse:u2|p_1~4013 music:mu|pulse:u2|p_1~4019sexp5 music:mu|pulse:u2|p_1[3] } { 0.000ns 2.000ns 0.000ns 0.000ns } { 0.000ns 8.000ns 8.000ns 6.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-18.000 ns - Smallest " "Info: - Smallest clock skew is -18.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in destination 3.000 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_in\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk_in 1 CLK PIN_83 55 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 55; CLK Node = 'clk_in'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_in } "NODE_NAME" } } { "bahe.vhd" "" { Text "D:/VHDL+拔河游戏机/bahe/bahe.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns music:mu\|pulse:u2\|p_1\[3\] 2 REG LC94 32 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC94; Fanout = 32; REG Node = 'music:mu\|pulse:u2\|p_1\[3\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.000 ns" { clk_in music:mu|pulse:u2|p_1[3] } "NODE_NAME" } } { "pulse.vhd" "" { Text "D:/VHDL+拔河游戏机/bahe/pulse.vhd" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 100.00 % ) " "Info: Total cell delay = 3.000 ns ( 100.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { clk_in music:mu|pulse:u2|p_1[3] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { clk_in clk_in~out music:mu|pulse:u2|p_1[3] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in source 21.000 ns - Longest register " "Info: - Longest clock path from clock \"clk_in\" to source register is 21.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk_in 1 CLK PIN_83 55 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 55; CLK Node = 'clk_in'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_in } "NODE_NAME" } } { "bahe.vhd" "" { Text "D:/VHDL+拔河游戏机/bahe/bahe.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns division:div\|clk2 2 REG LC50 14 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC50; Fanout = 14; REG Node = 'division:div\|clk2'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.000 ns" { clk_in division:div|clk2 } "NODE_NAME" } } { "division.vhd" "" { Text "D:/VHDL+拔河游戏机/bahe/division.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 13.000 ns division:div\|clk4 3 REG LC2 6 " "Info: 3: + IC(2.000 ns) + CELL(7.000 ns) = 13.000 ns; Loc. = LC2; Fanout = 6; REG Node = 'division:div\|clk4'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "9.000 ns" { division:div|clk2 division:div|clk4 } "NODE_NAME" } } { "division.vhd" "" { Text "D:/VHDL+拔河游戏机/bahe/division.vhd" 43 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 21.000 ns music:mu\|table:u1\|lpm_counter:counter_rtl_2\|dffs\[0\] 4 REG LC85 34 " "Info: 4: + IC(2.000 ns) + CELL(6.000 ns) = 21.000 ns; Loc. = LC85; Fanout = 34; REG Node = 'music:mu\|table:u1\|lpm_counter:counter_rtl_2\|dffs\[0\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { division:div|clk4 music:mu|table:u1|lpm_counter:counter_rtl_2|dffs[0] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "d:/altera/71/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "17.000 ns ( 80.95 % ) " "Info: Total cell delay = 17.000 ns ( 80.95 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns ( 19.05 % ) " "Info: Total interconnect delay = 4.000 ns ( 19.05 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "21.000 ns" { clk_in division:div|clk2 division:div|clk4 music:mu|table:u1|lpm_counter:counter_rtl_2|dffs[0] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "21.000 ns" { clk_in clk_in~out division:div|clk2 division:div|clk4 music:mu|table:u1|lpm_counter:counter_rtl_2|dffs[0] } { 0.000ns 0.000ns 0.000ns 2.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 7.000ns 6.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { clk_in music:mu|pulse:u2|p_1[3] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { clk_in clk_in~out music:mu|pulse:u2|p_1[3] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "21.000 ns" { clk_in division:div|clk2 division:div|clk4 music:mu|table:u1|lpm_counter:counter_rtl_2|dffs[0] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "21.000 ns" { clk_in clk_in~out division:div|clk2 division:div|clk4 music:mu|table:u1|lpm_counter:counter_rtl_2|dffs[0] } { 0.000ns 0.000ns 0.000ns 2.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 7.000ns 6.000ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" { } { { "lpm_counter.tdf" "" { Text "d:/altera/71/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" { } { { "pulse.vhd" "" { Text "D:/VHDL+拔河游戏机/bahe/pulse.vhd" 18 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "24.000 ns" { music:mu|table:u1|lpm_counter:counter_rtl_2|dffs[0] music:mu|pulse:u2|p_1~4013 music:mu|pulse:u2|p_1~4019sexp5 music:mu|pulse:u2|p_1[3] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "24.000 ns" { music:mu|table:u1|lpm_counter:counter_rtl_2|dffs[0] music:mu|pulse:u2|p_1~4013 music:mu|pulse:u2|p_1~4019sexp5 music:mu|pulse:u2|p_1[3] } { 0.000ns 2.000ns 0.000ns 0.000ns } { 0.000ns 8.000ns 8.000ns 6.000ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { clk_in music:mu|pulse:u2|p_1[3] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { clk_in clk_in~out music:mu|pulse:u2|p_1[3] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "21.000 ns" { clk_in division:div|clk2 division:div|clk4 music:mu|table:u1|lpm_counter:counter_rtl_2|dffs[0] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "21.000 ns" { clk_in clk_in~out division:div|clk2 division:div|clk4 music:mu|table:u1|lpm_counter:counter_rtl_2|dffs[0] } { 0.000ns 0.000ns 0.000ns 2.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 7.000ns 6.000ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "player1 register count:cnt\|lpm_counter:p1_rtl_0\|dffs\[0\] register count:cnt\|lpm_counter:p1_rtl_0\|dffs\[0\] 76.92 MHz 13.0 ns Internal " "Info: Clock \"player1\" has Internal fmax of 76.92 MHz between source register \"count:cnt\|lpm_counter:p1_rtl_0\|dffs\[0\]\" and destination register \"count:cnt\|lpm_counter:p1_rtl_0\|dffs\[0\]\" (period= 13.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.000 ns + Longest register register " "Info: + Longest register to register delay is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count:cnt\|lpm_counter:p1_rtl_0\|dffs\[0\] 1 REG LC21 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC21; Fanout = 10; REG Node = 'count:cnt\|lpm_counter:p1_rtl_0\|dffs\[0\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { count:cnt|lpm_counter:p1_rtl_0|dffs[0] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "d:/altera/71/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.000 ns) 8.000 ns count:cnt\|lpm_counter:p1_rtl_0\|dffs\[0\] 2 REG LC21 10 " "Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.000 ns; Loc. = LC21; Fanout = 10; REG Node = 'count:cnt\|lpm_counter:p1_rtl_0\|dffs\[0\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { count:cnt|lpm_counter:p1_rtl_0|dffs[0] count:cnt|lpm_counter:p1_rtl_0|dffs[0] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "d:/altera/71/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns ( 100.00 % ) " "Info: Total cell delay = 8.000 ns ( 100.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { count:cnt|lpm_counter:p1_rtl_0|dffs[0] count:cnt|lpm_counter:p1_rtl_0|dffs[0] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.000 ns" { count:cnt|lpm_counter:p1_rtl_0|dffs[0] count:cnt|lpm_counter:p1_rtl_0|dffs[0] } { 0.000ns 0.000ns } { 0.000ns 8.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "player1 destination 10.000 ns + Shortest register " "Info: + Shortest clock path from clock \"player1\" to destination register is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns player1 1 CLK PIN_84 5 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_84; Fanout = 5; CLK Node = 'player1'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { player1 } "NODE_NAME" } } { "bahe.vhd" "" { Text "D:/VHDL+拔河游戏机/bahe/bahe.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(6.000 ns) 10.000 ns count:cnt\|lpm_counter:p1_rtl_0\|dffs\[0\] 2 REG LC21 10 " "Info: 2: + IC(1.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC21; Fanout = 10; REG Node = 'count:cnt\|lpm_counter:p1_rtl_0\|dffs\[0\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { player1 count:cnt|lpm_counter:p1_rtl_0|dffs[0] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "d:/altera/71/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.000 ns ( 90.00 % ) " "Info: Total cell delay = 9.000 ns ( 90.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 10.00 % ) " "Info: Total interconnect delay = 1.000 ns ( 10.00 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { player1 count:cnt|lpm_counter:p1_rtl_0|dffs[0] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.000 ns" { player1 player1~out count:cnt|lpm_counter:p1_rtl_0|dffs[0] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 3.000ns 6.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "player1 source 10.000 ns - Longest register " "Info: - Longest clock path from clock \"player1\" to source register is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns player1 1 CLK PIN_84 5 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_84; Fanout = 5; CLK Node = 'player1'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { player1 } "NODE_NAME" } } { "bahe.vhd" "" { Text "D:/VHDL+拔河游戏机/bahe/bahe.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(6.000 ns) 10.000 ns count:cnt\|lpm_counter:p1_rtl_0\|dffs\[0\] 2 REG LC21 10 " "Info: 2: + IC(1.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC21; Fanout = 10; REG Node = 'count:cnt\|lpm_counter:p1_rtl_0\|dffs\[0\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { player1 count:cnt|lpm_counter:p1_rtl_0|dffs[0] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "d:/altera/71/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.000 ns ( 90.00 % ) " "Info: Total cell delay = 9.000 ns ( 90.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 10.00 % ) " "Info: Total interconnect delay = 1.000 ns ( 10.00 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { player1 count:cnt|lpm_counter:p1_rtl_0|dffs[0] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.000 ns" { player1 player1~out count:cnt|lpm_counter:p1_rtl_0|dffs[0] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 3.000ns 6.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { player1 count:cnt|lpm_counter:p1_rtl_0|dffs[0] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.000 ns" { player1 player1~out count:cnt|lpm_counter:p1_rtl_0|dffs[0] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 3.000ns 6.000ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { player1 count:cnt|lpm_counter:p1_rtl_0|dffs[0] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.000 ns" { player1 player1~out count:cnt|lpm_counter:p1_rtl_0|dffs[0] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 3.000ns 6.000ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" { } { { "lpm_counter.tdf" "" { Text "d:/altera/71/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" { } { { "lpm_counter.tdf" "" { Text "d:/altera/71/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { count:cnt|lpm_counter:p1_rtl_0|dffs[0] count:cnt|lpm_counter:p1_rtl_0|dffs[0] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.000 ns" { count:cnt|lpm_counter:p1_rtl_0|dffs[0] count:cnt|lpm_counter:p1_rtl_0|dffs[0] } { 0.000ns 0.000ns } { 0.000ns 8.000ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { player1 count:cnt|lpm_counter:p1_rtl_0|dffs[0] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.000 ns" { player1 player1~out count:cnt|lpm_counter:p1_rtl_0|dffs[0] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 3.000ns 6.000ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { player1 count:cnt|lpm_counter:p1_rtl_0|dffs[0] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.000 ns" { player1 player1~out count:cnt|lpm_counter:p1_rtl_0|dffs[0] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 3.000ns 6.000ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
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