pulse.vhd

带获胜音乐的拔河游戏机

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity pulse is
	port(clk:in std_logic;						--1MHz
		 count:in integer range 0 to 1300;		--发声控制
		 mus:out std_logic);					--蜂鸣器
end pulse;

architecture body_pulse of pulse is
	signal p_1:integer range 0 to 1300;
	signal pat,pat1,pat2,load:std_logic;

	begin
		process(clk,load,count)						--音乐控制
		begin
			if(clk'event and clk='1') then
				if(load='1') then p_1<=count;
				else p_1<=p_1-1;
				end if;
			end if;
		end process;
	
		process(p_1)								--节拍控制
		begin
			if(p_1=0) then pat<='1';
			else pat<='0';
			end if;
			load<=pat;
		end process;
	
		process(clk)
		begin
			if(clk'event and clk='1') then 
				pat1<=pat;
			end if;
		end process;

		process(pat1)
		begin 
			if(pat1'event and pat1='1') then 
				pat2<=not pat2;
			end if;
			mus<=pat2;
		end process;
	end body_pulse;