jpeg.h

最新MTK手机软件源码

#define JPEG_ENCODER_QUALITY_0_2		0x2
#define JPEG_ENCODER_QUALITY_0_1		0x1
#define JPEG_ENCODER_QUALITY_0_0		0x0
#define JPEG_ENCODER_QUALITY_1_3		0x7
#define JPEG_ENCODER_QUALITY_1_2		0x6
#define JPEG_ENCODER_QUALITY_1_1		0x5
#define JPEG_ENCODER_QUALITY_1_0		0x4
#define JPEG_ENCODER_QUALITY_2_3		0xB
#define JPEG_ENCODER_QUALITY_2_2		0xA
#define JPEG_ENCODER_QUALITY_2_1		0x9
#define JPEG_ENCODER_QUALITY_2_0		0x8
#define JPEG_ENCODER_QUALITY_3_3		0xF
#define JPEG_ENCODER_QUALITY_3_2		0xE
#define JPEG_ENCODER_QUALITY_3_1		0xD
#define JPEG_ENCODER_QUALITY_3_0		0xC

#define JPEG_ENCODER_HIGH_QUALITY	JPEG_ENCODER_QUALITY_0_3
#define JPEG_ENCODER_GOOD_QUALITY	JPEG_ENCODER_QUALITY_0_2
#define JPEG_ENCODER_FAIR_QUALITY	JPEG_ENCODER_QUALITY_0_1
#define JPEG_ENCODER_POOR_QUALITY	JPEG_ENCODER_QUALITY_0_0
#endif

#endif /*__SW_JPEG_CODEC_SUPPORT__*/

/* macros of JPEG encoder reset register */
#define RESET_JPEG_ENCODER		REG_JPEG_ENCODER_RESET = 1;\
										REG_JPEG_ENCODER_RESET = 0;
#define RELOAD_STALL_ADDRESS	REG_JPEG_ENCODER_RESET |= 0x10;

/* macros of JPEG encoder control register */
#define ENABLE_JPEG_ENCODER				REG_JPEG_ENCODER_CTRL |= JPEG_ENCODER_ENABLE_BIT;
#define SET_JPEG_ENCODER_COLOR_MODE		REG_JPEG_ENCODER_CTRL &= ~JPEG_ENCODER_GRAYSCALE_BIT;
#define SET_JPEG_ENCODER_GRAY_MODE		REG_JPEG_ENCODER_CTRL |= JPEG_ENCODER_GRAYSCALE_BIT;
#define ENABLE_JPEG_ENCODER_INT			REG_JPEG_ENCODER_CTRL |= JPEG_ENCODER_INT_ENABLE_BIT;
#define DISABLE_JPEG_ENCODER_INT			REG_JPEG_ENCODER_CTRL &= ~JPEG_ENCODER_INT_ENABLE_BIT;
#if (defined(JPEG_DRV_V3))
#define SET_JPEG_ENCODER_FORMAT_YUV422	REG_JPEG_ENCODER_CTRL &= ~JPEG_ENCODER_YUV_FORMAT_BIT;
#define SET_JPEG_ENCODER_FORMAT_YUV420	REG_JPEG_ENCODER_CTRL |= JPEG_ENCODER_YUV_FORMAT_BIT;
#define ENABLE_JPEG_ENCODER_JFIF_MODE	REG_JPEG_ENCODER_CTRL |= JPEG_ENCODER_APP_FORMAT_BIT;
#define DISABLE_JPEG_ENCODER_JFIF_MODE	REG_JPEG_ENCODER_CTRL &= ~JPEG_ENCODER_APP_FORMAT_BIT;
#define ENABLE_JPEG_ENCODER_CONT_SHOT	REG_JPEG_ENCODER_CTRL |= JPEG_ENCODER_CONT_SHOT_BIT;
#define DISABLE_JPEG_ENCODER_CONT_SHOT	REG_JPEG_ENCODER_CTRL &= ~JPEG_ENCODER_CONT_SHOT_BIT;
#define ENABLE_JPEG_ENCODER_ADDR_SWITCH	REG_JPEG_ENCODER_CTRL |= JPEG_ENCODER_ADDR_SWITCH_BIT;
#define DISABLE_JPEG_ENCODER_ADDR_SWITCH	REG_JPEG_ENCODER_CTRL &= ~JPEG_ENCODER_ADDR_SWITCH_BIT;
#endif

/* macros of JPEG encoder quality control register */
#define SET_JPEG_ENCODER_HIGH_QUALITY	REG_JPEG_ENCODER_QUALITY=JPEG_ENCODER_HIGH_QUALITY;
#define SET_JPEG_ENCODER_GOOD_QUALITY	REG_JPEG_ENCODER_QUALITY=JPEG_ENCODER_GOOD_QUALITY;
#define SET_JPEG_ENCODER_FAIR_QUALITY	REG_JPEG_ENCODER_QUALITY=JPEG_ENCODER_FAIR_QUALITY;
#define SET_JPEG_ENCODER_POOR_QUALITY	REG_JPEG_ENCODER_QUALITY=JPEG_ENCODER_POOR_QUALITY;
#define SET_JPEG_ENCODER_QUALITY(quality)		REG_JPEG_ENCODER_QUALITY=quality;

#define JPEG_ENCODER_IS_RUNNING 		(!(REG_JPEG_ENCODER_INT_STATUS & 0x01))
#endif /* MT6219 */

/* register definition of Resizer registers */
#if (defined(MT6218B))
#define RESIZER_CTRL_REG	   			(RESIZER_base + 0x00)
#define RESIZER_STATUS_REG				   (RESIZER_base + 0x04)
#define RESIZER_SOURCE_IMAGE_SIZE_REG	(RESIZER_base + 0x08)
#define RESIZER_TARGET_IMAGE_SIZE_REG	(RESIZER_base + 0x0C)
#define RESIZER_BLOCK_CS_CFG_REG		   (RESIZER_base + 0x10)
#define RESIZER_Y_LINE_BUFFER_ADDR_REG	(RESIZER_base + 0x14)
#define RESIZER_U_LINE_BUFFER_ADDR_REG	(RESIZER_base + 0x18)
#define RESIZER_V_LINE_BUFFER_ADDR_REG	(RESIZER_base + 0x1C)
#define RESIZER_FINE_RESIZE_CFG_REG		(RESIZER_base + 0x20)
#define RESIZER_Y_WORK_MEM_ADDR_REG		(RESIZER_base + 0x24)
#define RESIZER_U_WORK_MEM_ADDR_REG		(RESIZER_base + 0x28)
#define RESIZER_V_WORK_MEM_ADDR_REG		(RESIZER_base + 0x2C)
#define RESIZER_YUV2RGB_CFG_REG			(RESIZER_base + 0x30)
#define RESIZER_TARGET_MEM_ADDR_REG		(RESIZER_base + 0x34)
#define RESIZER_LINE_BUFFER_SIZE_REG	(RESIZER_base + 0x38)
#define RESIZER_YUV2RGB_INT_STATUS_REG	(RESIZER_base + 0x40)

#define REG_RESIZER_CTRL			   	*((volatile unsigned int *) (RESIZER_base + 0x00))
#define REG_RESIZER_STATUS				   *((volatile unsigned int *) (RESIZER_base + 0x04))
#define REG_RESIZER_SOURCE_IMAGE_SIZE	*((volatile unsigned int *) (RESIZER_base + 0x08))
#define REG_RESIZER_TARGET_IMAGE_SIZE	*((volatile unsigned int *) (RESIZER_base + 0x0C))
#define REG_RESIZER_BLOCK_CS_CFG		   *((volatile unsigned int *) (RESIZER_base + 0x10))
#define REG_RESIZER_Y_LINE_BUFFER_ADDR	*((volatile unsigned int *) (RESIZER_base + 0x14))
#define REG_RESIZER_U_LINE_BUFFER_ADDR	*((volatile unsigned int *) (RESIZER_base + 0x18))
#define REG_RESIZER_V_LINE_BUFFER_ADDR	*((volatile unsigned int *) (RESIZER_base + 0x1C))
#define REG_RESIZER_FINE_RESIZE_CFG		*((volatile unsigned int *) (RESIZER_base + 0x20))
#define REG_RESIZER_Y_WORK_MEM_ADDR		*((volatile unsigned int *) (RESIZER_base + 0x24))
#define REG_RESIZER_U_WORK_MEM_ADDR		*((volatile unsigned int *) (RESIZER_base + 0x28))
#define REG_RESIZER_V_WORK_MEM_ADDR		*((volatile unsigned int *) (RESIZER_base + 0x2C))
#define REG_RESIZER_YUV2RGB_CFG			*((volatile unsigned int *) (RESIZER_base + 0x30))
#define REG_RESIZER_TARGET_MEM_ADDR		*((volatile unsigned int *) (RESIZER_base + 0x34))
#define REG_RESIZER_LINE_BUFFER_SIZE	*((volatile unsigned int *) (RESIZER_base + 0x38))
#define REG_RESIZER_YUV2RGB_INT_STATUS	*((volatile unsigned int *) (RESIZER_base + 0x40))

/* bit mapping of resizer control register */
#define RESIZER_CTRL_RESET_MASK                 0x00070000
#define RESIZER_CTRL_ENABLE_MASK                0x00000007
#define RESIZER_CTRL_BLOCK_CS_ENABLE_BIT		   0x00000001
#define RESIZER_CTRL_FINE_RESIZE_ENABLE_BIT		0x00000002
#define RESIZER_CTRL_YUV2RGB_ENABLE_BIT			0x00000004
#define RESIZER_CTRL_BLOCK_CS_RESET_BIT			0x00010000
#define RESIZER_CTRL_FINE_RESIZE_RESET_BIT		0x00020000
#define RESIZER_CTRL_YUV2RGB_RESET_BIT			   0x00040000

/* bit mapping of resizer status register */
#define RESIZER_CTRL_BLOCK_CS_BUSY_BIT			0x00000001
#define RESIZER_CTRL_FINE_RESIZE_BUSY_BIT		0x00000002
#define RESIZER_CTRL_YUV2RGB_BUSY_BIT			0x00000004

/* bit mapping of resizer source and target size register */
#define RESIZER_IMAGE_SIZE_WIDTH_MASK			0x000003FF
#define RESIZER_IMAGE_SIZE_HEIGHT_MASK			0x01FF0000

/* bit mapping of resizer block coarse shrink config register */
#define RESIZER_BLOCk_CS_CFG_V_V_SAMPLE_FACTOR_MASK	0x0000C000
#define RESIZER_BLOCk_CS_CFG_V_H_SAMPLE_FACTOR_MASK	0x00003000
#define RESIZER_BLOCk_CS_CFG_U_V_SAMPLE_FACTOR_MASK	0x00000C00
#define RESIZER_BLOCk_CS_CFG_U_H_SAMPLE_FACTOR_MASK	0x00000300
#define RESIZER_BLOCk_CS_CFG_Y_V_SAMPLE_FACTOR_MASK	0x000000C0
#define RESIZER_BLOCk_CS_CFG_Y_H_SAMPLE_FACTOR_MASK	0x00000030
#define RESIZER_BLOCk_CS_CFG_PLC_MASK				      0x0000000C
#define RESIZER_BLOCk_CS_CFG_CS_FACTOR_MASK			   0x00000003

/* definition of resizer block CS register */
#define BLOCK_CS_1_1			   0x00000000
#define BLOCK_CS_1_4			   0x00000001
#define BLOCK_CS_1_16			0x00000002
#define BLOCK_CS_1_64			0x00000003
#define BLOCK_PLC_0				0x00000000
#define BLOCK_PLC_1				0x00000004
#define BLOCK_Y_H_FACTOR_1		0x00000000
#define BLOCK_Y_H_FACTOR_2		0x00000010
#define BLOCK_Y_H_FACTOR_4		0x00000020
#define BLOCK_Y_V_FACTOR_1		0x00000000
#define BLOCK_Y_V_FACTOR_2		0x00000040
#define BLOCK_Y_V_FACTOR_4		0x00000080
#define BLOCK_U_H_FACTOR_1		0x00000000
#define BLOCK_U_H_FACTOR_2		0x00000100
#define BLOCK_U_H_FACTOR_4		0x00000200
#define BLOCK_U_V_FACTOR_1		0x00000000
#define BLOCK_U_V_FACTOR_2		0x00000400
#define BLOCK_U_V_FACTOR_4		0x00000800
#define BLOCK_V_H_FACTOR_1		0x00000000
#define BLOCK_V_H_FACTOR_2		0x00001000
#define BLOCK_V_H_FACTOR_4		0x00002000
#define BLOCK_V_V_FACTOR_1		0x00000000
#define BLOCK_V_V_FACTOR_2		0x00004000
#define BLOCK_V_V_FACTOR_4		0x00008000

/* bit mapping of resizer fine resize config register */
#define RESIZER_FINE_RESIZE_WORK_MEM_SIZE_MASK	0x03FF0000
#define RESIZER_FINE_RESIZE_SEQ_BIT				   0x00008000
#define RESIZER_FINE_RESIZE_HR_SRC_MASK			0x0000000C
#define RESIZER_FINE_RESIZE_PLC_MASK			   0x00000003

/* definition of fine resize config register */
#define FINE_RESIZE_HR_SRC_BLOCK_CS	0x00000000
#define FINE_RESIZE_HR_SRC_MEM		0x00000004
#define FINE_RESIZE_PLC_00			   0x00000000
#define FINE_RESIZE_PLC_01			   0x00000001

/* bit mapping of YUV2RGB config register */
#define RESIZER_YUV2RGB_INT_ENABLE_BIT	0x00008000
#define RESIZER_YUV2RGB_SRC_BIT			0x00000001

/* bit mapping of resizer line buffer size register */
#define RESIZER_BLOCk_CS_Y_LINE_BUFF_SIZE_MASK	0x000003FF
#define RESIZER_BLOCk_CS_U_LINE_BUFF_SIZE_MASK	0x000FFC00
#define RESIZER_BLOCk_CS_V_LINE_BUFF_SIZE_MASK	0x3FF00000

/* bit mapping of image resizer interupt status register */
#define RESIZER_YUV2RGB_INT_STATUS_BIT	0x00000001

/* Macros of resizer control register */
#define RESET_RESIZER               REG_RESIZER_CTRL=RESIZER_CTRL_RESET_MASK;\
                                    REG_RESIZER_CTRL=0;
#define SET_BLOCK_CS_RESET		   	REG_RESIZER_CTRL |= RESIZER_CTRL_BLOCK_CS_RESET_BIT;
#define CLEAR_BLOCK_CS_RESET		   REG_RESIZER_CTRL &= ~RESIZER_CTRL_BLOCK_CS_RESET_BIT;
#define SET_FINE_RESIZE_RESET		   REG_RESIZER_CTRL |= RESIZER_CTRL_FINE_RESIZE_RESET_BIT;
#define CLEAR_FINE_RESIZE_RESET  	REG_RESIZER_CTRL &= ~RESIZER_CTRL_FINE_RESIZE_RESET_BIT;
#define SET_YUV2RGB_RESET			   REG_RESIZER_CTRL |= RESIZER_CTRL_YUV2RGB_RESET_BIT;
#define CLEAR_YUV2RGB_RESET			REG_RESIZER_CTRL &= ~RESIZER_CTRL_YUV2RGB_RESET_BIT;
#define ENABLE_BLOCK_CS_BLOCK		   REG_RESIZER_CTRL |= RESIZER_CTRL_BLOCK_CS_ENABLE_BIT
#define DISABLE_BLOCK_CS_BLOCK		REG_RESIZER_CTRL &= ~RESIZER_CTRL_BLOCK_CS_ENABLE_BIT
#define ENABLE_FINE_RESIZE_BLOCK	   REG_RESIZER_CTRL |= RESIZER_CTRL_FINE_RESIZE_ENABLE_BIT
#define DISABLE_FINE_RESIZE_BLOCK	REG_RESIZER_CTRL &= ~RESIZER_CTRL_FINE_RESIZE_ENABLE_BIT
#define ENABLE_YUV2RGB_BLOCK		   REG_RESIZER_CTRL |= RESIZER_CTRL_YUV2RGB_ENABLE_BIT
#define DISABLE_YUV2RGB_BLOCK	   	REG_RESIZER_CTRL &= ~RESIZER_CTRL_YUV2RGB_ENABLE_BIT
#define ENABLE_RESIZER              REG_RESIZER_CTRL = RESIZER_CTRL_ENABLE_MASK;

/* Macros of resizer status register */
#define IS_BLOCK_CS_BUSY		 (REG_RESIZER_STATUS & RESIZER_CTRL_BLOCK_CS_BUSY_BIT)
#define IS_FINE_RESIZE_BUSY	 (REG_RESIZER_STATUS & RESIZER_CTRL_FINE_RESIZE_BUSY_BIT)
#define IS_YUV2RGB_BUSY			 (REG_RESIZER_STATUS & RESIZER_CTRL_YUV2RGB_BUSY_BIT)

/* Macros of resizer source image size register */
#define SET_RESIZER_SRC_SIZE(width, height)		REG_RESIZER_SOURCE_IMAGE_SIZE=(width|(height<<16));

/* Macros of resizer target image size register */
#define SET_RESIZER_TARGET_SIZE(width, height)	REG_RESIZER_TARGET_IMAGE_SIZE=(width|(height<<16));

/* Macros of resizer block coarse shrinking config register */
#define SET_RESIZER_BLOCK_CS_V_V_FACTOR(factor)		REG_RESIZER_BLOCK_CS_CFG &= ~RESIZER_BLOCk_CS_CFG_V_V_SAMPLE_FACTOR_MASK;\
										            			REG_RESIZER_BLOCK_CS_CFG |= ((factor>>1)<<14);
#define SET_RESIZER_BLOCK_CS_V_H_FACTOR(factor)		REG_RESIZER_BLOCK_CS_CFG &= ~RESIZER_BLOCk_CS_CFG_V_H_SAMPLE_FACTOR_MASK;\
													            REG_RESIZER_BLOCK_CS_CFG |= ((factor>>1)<<12);
#define SET_RESIZER_BLOCK_CS_U_V_FACTOR(factor)		REG_RESIZER_BLOCK_CS_CFG &= ~RESIZER_BLOCk_CS_CFG_U_V_SAMPLE_FACTOR_MASK;\
													            REG_RESIZER_BLOCK_CS_CFG |= ((factor>>1)<<10);
#define SET_RESIZER_BLOCK_CS_U_H_FACTOR(factor)		REG_RESIZER_BLOCK_CS_CFG &= ~RESIZER_BLOCk_CS_CFG_U_H_SAMPLE_FACTOR_MASK;\
													            REG_RESIZER_BLOCK_CS_CFG |= ((factor>>1)<<8);
#define SET_RESIZER_BLOCK_CS_Y_V_FACTOR(factor)		REG_RESIZER_BLOCK_CS_CFG &= ~RESIZER_BLOCk_CS_CFG_Y_V_SAMPLE_FACTOR_MASK;\
            													REG_RESIZER_BLOCK_CS_CFG |= ((factor>>1)<<6);
#define SET_RESIZER_BLOCK_CS_Y_H_FACTOR(factor)		REG_RESIZER_BLOCK_CS_CFG &= ~RESIZER_BLOCk_CS_CFG_Y_H_SAMPLE_FACTOR_MASK;\
				            									REG_RESIZER_BLOCK_CS_CFG |= ((factor>>1)<<4);
#define SET_RESIZER_BLOCK_CS_PLC(plc)		   		REG_RESIZER_BLOCK_CS_CFG &= ~RESIZER_BLOCk_CS_CFG_PLC_MASK;\
								            					REG_RESIZER_BLOCK_CS_CFG |= plc;
#define SET_RESIZER_BLOCK_CS_FACTOR(factor)			REG_RESIZER_BLOCK_CS_CFG &= ~RESIZER_BLOCk_CS_CFG_CS_FACTOR_MASK;\
													            REG_RESIZER_BLOCK_CS_CFG |= factor;

/* macros of resizer fine resizer config register */
#define SET_RESIZER_FINE_RESIZE_WORK_MEM_SIZE(line)	REG_RESIZER_FINE_RESIZE_CFG &= ~RESIZER_FINE_RESIZE_WORK_MEM_SIZE_MASK;\
               													REG_RESIZER_FINE_RESIZE_CFG |= (line<<16);
#define SET_RESIZER_FINE_RESIZE_HR_SRC_MEM   			REG_RESIZER_FINE_RESIZE_CFG &= ~RESIZER_FINE_RESIZE_HR_SRC_MASK;\
					               								REG_RESIZER_FINE_RESIZE_CFG |= RESIZER_FINE_RESIZE_HR_SRC_MEM;
#define SET_RESIZER_FINE_RESIZE_HR_SRC_BLOCK_CS 		REG_RESIZER_FINE_RESIZE_CFG &= ~RESIZER_FINE_RESIZE_HR_SRC_MASK;
#define SET_RESIZER_FINE_RESIZE_PLC(plc)			      REG_RESIZER_FINE_RESIZE_CFG &= ~RESIZER_FINE_RESIZE_PLC_MASK;\
               													REG_RESIZER_FINE_RESIZE_CFG |= plc;
#define ENABLE_RESIZER_FINE_RESIZE_SEQ	      			REG_RESIZER_FINE_RESIZE_CFG |= RESIZER_FINE_RESIZE_SEQ_BIT;
#define DISABLE_RESIZER_FIEN_RESIZE_SEQ		   		REG_RESIZER_FINE_RESIZE_CFG &= ~RESIZER_FINE_RESIZE_SEQ_BIT;


/* macros of resizer YUV2RGB config register */
#define ENABLE_RESIZER_YUV2RGB_INT		REG_RESIZER_YUV2RGB_CFG |= RESIZER_YUV2RGB_INT_ENABLE_BIT;
#define DISABLE_RESIZER_YUV2RGB_INT		REG_RESIZER_YUV2RGB_CFG &= ~RESIZER_YUV2RGB_INT_ENABLE_BIT;

/* macros of resizer line buffer size register */
#define SET_RESIZER_FINE_RESIZE_Y_LINE_BUFFER(n)	REG_RESIZER_LINE_BUFFER_SIZE &= ~RESIZER_BLOCk_CS_Y_LINE_BUFF_SIZE_MASK; \
            													REG_RESIZER_LINE_BUFFER_SIZE |= n;
#define SET_RESIZER_FINE_RESIZE_U_LINE_BUFFER(n)	REG_RESIZER_LINE_BUFFER_SIZE &= ~RESIZER_BLOCk_CS_U_LINE_BUFF_SIZE_MASK; \
				            									REG_RESIZER_LINE_BUFFER_SIZE |= (n<<10);
#define SET_RESIZER_FINE_RESIZE_V_LINE_BUFFER(n)	REG_RESIZER_LINE_BUFFER_SIZE &= ~RESIZER_BLOCk_CS_V_LINE_BUFF_SIZE_MASK; \
								            					REG_RESIZER_LINE_BUFFER_SIZE |= (n<<20);

/* macros of resizer interrupt status register */
#define IS_RESIZER_COMPLETE_INT		(REG_RESIZER_YUV2RGB_INT_STATUS & RESIZER_YUV2RGB_INT_STATUS_BIT)

#elif (defined(MT6217))
#define RESIZER_CONFIG_REG	   			(RESIZER_base + 0x00)
#define RESIZER_CTRL_REG	   			(RESIZER_base + 0x04)
#define RESIZER_STATUS_REG				   (RESIZER_base + 0x08)
#define RESIZER_INT_STATUS_REG			(RESIZER_base + 0x0C)
#define RESIZER_SOURCE_IMAGE_SIZE_REG	(RESIZER_base + 0x10)
#define RESIZER_TARGET_IMAGE_SIZE_REG	(RESIZER_base + 0x14)
#define RESIZER_H_RATIO_REG				(RESIZER_base + 0x18)
#define RESIZER_V_RATIO_REG				(RESIZER_base + 0x1C)
#define RESIZER_H_RESIDUAL_REG			(RESIZER_base + 0x20)
#define RESIZER_V_RESIDUAL_REG			(RESIZER_base + 0x24)
#define RESIZER_BLOCK_CS_CFG_REG		   (RESIZER_base + 0x30)
#define RESIZER_Y_LINE_BUFFER_ADDR_REG	(RESIZER_base + 0x34)
#define RESIZER_U_LINE_BUFFER_ADDR_REG	(RESIZER_base + 0x38)
#define RESIZER_V_LINE_BUFFER_ADDR_REG	(RESIZER_base + 0x3C)
#define RESIZER_FINE_RESIZE_CFG_REG		(RESIZER_base + 0x40)
#define RESIZER_LINE_BUFFER_SIZE			(RESIZER_base + 0x50)
#define RESIZER_WORK_MEM_ADDR_REG		(RESIZER_base + 0x5C)
#define RESIZER_YUV2RGB_CFG_REG			(RESIZER_base + 0x80)
#define RESIZER_TARGET_MEM_ADDR_REG		(RESIZER_base + 0x84)

#define REG_RESIZER_CONFIG			   	*((volatile unsigned int *) (RESIZER_base + 0x00))
#define REG_RESIZER_CTRL			   	*((volatile unsigned int *) (RESIZER_base + 0x04))