📄 isp_if.h
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#define REG_SPACE_CVT_YUV_U_GAIN_MASK 0x0000FF00
#define REG_SPACE_CVT_YUV_V_GAIN_MASK 0x000000FF
#define REG_SPACE_CVT_YUV_Y_OFFSET_MASK 0x00FF0000
#define REG_SPACE_CVT_YUV_U_OFFSET_MASK 0x0000FF00
#define REG_SPACE_CVT_YUV_V_OFFSET_MASK 0x000000FF
/* bit mapping of Gamma operation register 1~3 */
#define REG_GAMMA_OPERATION_GAMMA_B1_MASK 0xFF000000
#define REG_GAMMA_OPERATION_GAMMA_B2_MASK 0x00FF0000
#define REG_GAMMA_OPERATION_GAMMA_B3_MASK 0x0000FF00
#define REG_GAMMA_OPERATION_GAMMA_B4_MASK 0x000000FF
#define REG_GAMMA_OPERATION_GAMMA_B5_MASK 0xFF000000
#define REG_GAMMA_OPERATION_GAMMA_B6_MASK 0x00FF0000
#define REG_GAMMA_OPERATION_GAMMA_B7_MASK 0x0000FF00
#define REG_GAMMA_OPERATION_GAMMA_B8_MASK 0x000000FF
#define REG_GAMMA_OPERATION_GAMMA_B9_MASK 0xFF000000
#define REG_GAMMA_OPERATION_GAMMA_B10_MASK 0x00FF0000
#define REG_GAMMA_OPERATION_GAMMA_B11_MASK 0x0000FF00
/* bit mapping of 1024 Gamma table */
#define REG_GAMMA_OPERATION_1024_ENABLE_BIT 0x00000001
#define INTMEM_GAMMA_1024_BYTE1_MASK 0xFF000000
#define INTMEM_GAMMA_1024_BYTE2_MASK 0x00FF0000
#define INTMEM_GAMMA_1024_BYTE3_MASK 0x0000FF00
#define INTMEM_GAMMA_1024_BYTE4_MASK 0x000000FF
#if (defined(MT6226)||defined(MT6226M)||defined(MT6227)||defined(MT6228)||defined(MT6229)||defined(MT6230))
/* bit mapping of Sensor Gamma R register 1~3 */
#define REG_SENSOR_GAMMA_ENABLE_MASK 0x10000000
#define REG_SENSOR_GAMMA_IVT_MASK 0x01000000
#define REG_SENSOR_GAMMA_R_B1_MASK 0x00FF0000
#define REG_SENSOR_GAMMA_R_B2_MASK 0x0000FF00
#define REG_SENSOR_GAMMA_R_B3_MASK 0x000000FF
#define REG_SENSOR_GAMMA_R_B4_MASK 0xFF000000
#define REG_SENSOR_GAMMA_R_B5_MASK 0x00FF0000
#define REG_SENSOR_GAMMA_R_B6_MASK 0x0000FF00
#define REG_SENSOR_GAMMA_R_B7_MASK 0x000000FF
#define REG_SENSOR_GAMMA_R_B8_MASK 0xFF000000
#define REG_SENSOR_GAMMA_R_B9_MASK 0x00FF0000
#define REG_SENSOR_GAMMA_R_B10_MASK 0x0000FF00
#define REG_SENSOR_GAMMA_R_B11_MASK 0x000000FF
#if(!(defined(MT6227)||defined(MT6229)||defined(MT6230)))
/* bit mapping of Sensor Gamma G register 1~3 */
#define REG_SENSOR_GAMMA_G_B1_MASK 0xFF000000
#define REG_SENSOR_GAMMA_G_B2_MASK 0x00FF0000
#define REG_SENSOR_GAMMA_G_B3_MASK 0x0000FF00
#define REG_SENSOR_GAMMA_G_B4_MASK 0x000000FF
#define REG_SENSOR_GAMMA_G_B5_MASK 0xFF000000
#define REG_SENSOR_GAMMA_G_B6_MASK 0x00FF0000
#define REG_SENSOR_GAMMA_G_B7_MASK 0x0000FF00
#define REG_SENSOR_GAMMA_G_B8_MASK 0x000000FF
#define REG_SENSOR_GAMMA_G_B9_MASK 0xFF000000
#define REG_SENSOR_GAMMA_G_B10_MASK 0x00FF0000
#define REG_SENSOR_GAMMA_G_B11_MASK 0x0000FF00
#endif
#if(defined(MT6227)||defined(MT6229)||defined(MT6230))
/* bit mapping of Sensor Gamma G register 1~3 */
#define REG_SENSOR_GAMMA_GR_B1_MASK 0xFF000000
#define REG_SENSOR_GAMMA_GR_B2_MASK 0x00FF0000
#define REG_SENSOR_GAMMA_GR_B3_MASK 0x0000FF00
#define REG_SENSOR_GAMMA_GR_B4_MASK 0x000000FF
#define REG_SENSOR_GAMMA_GR_B5_MASK 0xFF000000
#define REG_SENSOR_GAMMA_GR_B6_MASK 0x00FF0000
#define REG_SENSOR_GAMMA_GR_B7_MASK 0x0000FF00
#define REG_SENSOR_GAMMA_GR_B8_MASK 0x000000FF
#define REG_SENSOR_GAMMA_GR_B9_MASK 0xFF000000
#define REG_SENSOR_GAMMA_GR_B10_MASK 0x00FF0000
#define REG_SENSOR_GAMMA_GR_B11_MASK 0x0000FF00
#define REG_SENSOR_GAMMA_GB_B1_MASK 0xFF000000
#define REG_SENSOR_GAMMA_GB_B2_MASK 0x00FF0000
#define REG_SENSOR_GAMMA_GB_B3_MASK 0x0000FF00
#define REG_SENSOR_GAMMA_GB_B4_MASK 0x000000FF
#define REG_SENSOR_GAMMA_GB_B5_MASK 0xFF000000
#define REG_SENSOR_GAMMA_GB_B6_MASK 0x00FF0000
#define REG_SENSOR_GAMMA_GB_B7_MASK 0x0000FF00
#define REG_SENSOR_GAMMA_GB_B8_MASK 0x000000FF
#define REG_SENSOR_GAMMA_GB_B9_MASK 0xFF000000
#define REG_SENSOR_GAMMA_GB_B10_MASK 0x00FF0000
#define REG_SENSOR_GAMMA_GB_B11_MASK 0x0000FF00
#endif
/* bit mapping of Sensor Gamma B register 1~3 */
#define REG_SENSOR_GAMMA_B_B1_MASK 0xFF000000
#define REG_SENSOR_GAMMA_B_B2_MASK 0x00FF0000
#define REG_SENSOR_GAMMA_B_B3_MASK 0x0000FF00
#define REG_SENSOR_GAMMA_B_B4_MASK 0x000000FF
#define REG_SENSOR_GAMMA_B_B5_MASK 0xFF000000
#define REG_SENSOR_GAMMA_B_B6_MASK 0x00FF0000
#define REG_SENSOR_GAMMA_B_B7_MASK 0x0000FF00
#define REG_SENSOR_GAMMA_B_B8_MASK 0x000000FF
#define REG_SENSOR_GAMMA_B_B9_MASK 0xFF000000
#define REG_SENSOR_GAMMA_B_B10_MASK 0x00FF0000
#define REG_SENSOR_GAMMA_B_B11_MASK 0x0000FF00
/* bit mapping of defect pixel register */
#define REG_DEFECT_ENABLE_BIT 0x01000000
/* ae area register */
#define REG_AE_AREACNT_MASK 0x0000003F
#define REG_AE_FRAMECNT_MASK 0x0000FF00
#define REG_AE_HOFFSET_MASK 0x00FF0000
#define REG_AE_VOFFSET_MASK 0xFF000000
#endif
/* bit mapping of LPF control register */
#if (defined(MT6219))
#define REG_LPF_Y_LPF_ENABLE_BIT 0x00004000
#define REG_LPF_Y_LPF_TYPE_MASK 0x00003000
#define REG_LPF_C_LPF_ENABLE_BIT 0x00000800
#define REG_LPF_C_LPF_TYPE_MASK 0x00000600
#define REG_LPF_SUB_SAMPLE_MASK 0x00000007
#define REG_LPF_SUB_SAMPLE_1_8 0x00000004
#define REG_LPF_SUB_SAMPLE_1_4 0x00000002
#define REG_LPF_SUB_SAMPLE_1_2 0x00000001
#define REG_LPF_SUB_SAMPLE_1_1 0x00000000
#elif (defined(MT6226)||defined(MT6226M)||defined(MT6227)||defined(MT6228)||defined(MT6229)||defined(MT6230))
#define REG_LPF_V_LPF_ENABLE_BIT 0x00010000
#define REG_LPF_Y_LPF_ENABLE_BIT 0x00008000
#define REG_LPF_C_LPF_ENABLE_BIT 0x00001000
/* bit mapping of Y LPF control register */
#define REG_Y_LPF_WEIGHT0_MASK 0xFF000000
#define REG_Y_LPF_WEIGHT1_MASK 0x00FF0000
#define REG_Y_LPF_WEIGHT2_MASK 0x0000FF00
#define REG_Y_LPF_WEIGHT3_MASK 0x000000FF
/* bit mapping of CBCR LPF control register */
#define REG_C_LPF_WEIGHT0_MASK 0xFF000000
#define REG_C_LPF_WEIGHT1_MASK 0x00FF0000
#define REG_C_LPF_WEIGHT2_MASK 0x0000FF00
#define REG_C_LPF_WEIGHT3_MASK 0x000000FF
/* bit mapping of vertical sub-sample control register */
#define REG_VERTICAL_SUB_V_SUB_EN_BIT 0x10000000
#define REG_VERTICAL_SUB_V_SUB_IN_MASK 0x0FFF0000
#define REG_VERTICAL_SUB_V_SUB_OUT_MASK 0x00000FFF
/* bit mapping of horizontal sub-sample control register */
#define REG_HORIZONTAL_SUB_H_SUB_EN_BIT 0x10000000
#define REG_HORIZONTAL_SUB_H_SUB_IN_MASK 0x0FFF0000
#define REG_HORIZONTAL_SUB_H_SUB_OUT_MASK 0x00000FFF
#endif
#if (!(defined(MT6219)||defined(MT6228)))
/* bit mapping of result window register */
#define REG_RESULT_WINDOW_ENABLE_BIT 0x10000000
#define REG_RESULT_WINDOW_START_MASK 0x0FFF0000
#define REG_RESULT_WINDOW_END_MASK 0x00000FFF
#endif
/* bit mapping of Camera interface debug mode control register */
#define REG_DEBUG_GMC_ENABLE_BIT 0x00000080
#define REG_DEBUG_GMC_MODE_BIT 0x00000040
#define REG_DEBUG_DATA_COUNT_ENABLE_BIT 0x00000020
#define REG_DEBUG_DATA_COUNT_MODE_MASK 0x00000018
#define REG_DEBUG_RAW_RGB_OUTPUT_COUNT 0
#define REG_DEBUG_YCBCR_OUPUT_COUNT 1
#define REG_DEBUG_GMC_OUTPUT_COUNT 2
#define REG_DEBUG_RESIZER_ACK_COUNT 3
#if (defined(MT6226)||defined(MT6226M)||defined(MT6227)||defined(MT6228)||defined(MT6229)||defined(MT6230))
/* bit mapping of shading control register */
#define REG_SHADING_RANGE_ENABLE_BIT 0x20000000
#define REG_SHADING_ENABLE_BIT 0x10000000
#define REG_SHADING_CENTERY_MASK 0x0FFF0000
#define REG_SHADING_K_FACTOR_MASK 0x0000C000
#define REG_SHADING_RADIUS_FACTOR_MASK 0x00003000
#define REG_SHADING_CENTERX_MASK 0x00000FFF
#define REG_SHADING_KR_MASK 0xFF000000
#define REG_SHADING_KG_MASK 0x00FF0000
#define REG_SHADING_KB_MASK 0x0000FF00
#define REG_SHADING_RANGE_MASK 0x000000FF
#define REG_SHADING_CURVE_ENABLE_BIT 0x10000000
#define REG_SHADING_CURVE_IVT_MASK 0x04000000
#define REG_SHADING_CURVE_SEL_MASK 0x03000000
#define REG_SHADING_CURVE_R_B1_MASK 0x00FF0000
#define REG_SHADING_CURVE_R_B2_MASK 0x0000FF00
#define REG_SHADING_CURVE_R_B3_MASK 0x000000FF
#define REG_SHADING_CURVE_R_B4_MASK 0xFF000000
#define REG_SHADING_CURVE_R_B5_MASK 0x00FF0000
#define REG_SHADING_CURVE_R_B6_MASK 0x0000FF00
#define REG_SHADING_CURVE_R_B7_MASK 0x000000FF
#define REG_SHADING_CURVE_R_B8_MASK 0xFF000000
#define REG_SHADING_CURVE_R_B9_MASK 0x00FF0000
#define REG_SHADING_CURVE_R_B10_MASK 0x0000FF00
#define REG_SHADING_CURVE_R_B11_MASK 0x000000FF
#define REG_SHADING_CURVE_G_B1_MASK 0xFF000000
#define REG_SHADING_CURVE_G_B2_MASK 0x00FF0000
#define REG_SHADING_CURVE_G_B3_MASK 0x0000FF00
#define REG_SHADING_CURVE_G_B4_MASK 0x000000FF
#define REG_SHADING_CURVE_G_B5_MASK 0xFF000000
#define REG_SHADING_CURVE_G_B6_MASK 0x00FF0000
#define REG_SHADING_CURVE_G_B7_MASK 0x0000FF00
#define REG_SHADING_CURVE_G_B8_MASK 0x000000FF
#define REG_SHADING_CURVE_G_B9_MASK 0xFF000000
#define REG_SHADING_CURVE_G_B10_MASK 0x00FF0000
#define REG_SHADING_CURVE_G_B11_MASK 0x0000FF00
#define REG_SHADING_CURVE_B_B1_MASK 0xFF000000
#define REG_SHADING_CURVE_B_B2_MASK 0x00FF0000
#define REG_SHADING_CURVE_B_B3_MASK 0x0000FF00
#define REG_SHADING_CURVE_B_B4_MASK 0x000000FF
#define REG_SHADING_CURVE_B_B5_MASK 0xFF000000
#define REG_SHADING_CURVE_B_B6_MASK 0x00FF0000
#define REG_SHADING_CURVE_B_B7_MASK 0x0000FF00
#define REG_SHADING_CURVE_B_B8_MASK 0x000000FF
#define REG_SHADING_CURVE_B_B9_MASK 0xFF000000
#define REG_SHADING_CURVE_B_B10_MASK 0x00FF0000
#define REG_SHADING_CURVE_B_B11_MASK 0x0000FF00
#endif
#if (defined(MT6228)||defined(MT6229)||defined(MT6230))
/* bit mapping of AE window size register */
#define REG_AE_VSIZE_MASK 0xFFFF0000
#define REG_AE_HSIZE_MASK 0x0000FFFF
/* bit mapping of AE weight register */
#define REG_AE_WEIGHT00_MASK 0xF0000000
#define REG_AE_WEIGHT01_MASK 0x0F000000
#define REG_AE_WEIGHT02_MASK 0x00F00000
#define REG_AE_WEIGHT03_MASK 0x000F0000
#define REG_AE_WEIGHT04_MASK 0x0000F000
#define REG_AE_WEIGHT05_MASK 0x00000F00
#define REG_AE_WEIGHT06_MASK 0x000000F0
#define REG_AE_WEIGHT07_MASK 0x0000000F
#endif
#if (defined(MT6226)||defined(MT6226M)||defined(MT6227)||defined(MT6228)||defined(MT6229)||defined(MT6230))
/* bit mapping of auto defect control register */
#define REG_AUTO_DEFECT_CTRL1_BIT31_16_MASK 0xFFFF0000
#define REG_AUTO_DEFECT_ADC_EN_BIT 0x80000000
#define REG_AUTO_DEFECT_ADL_EN_BIT 0x40000000
#define REG_AUTO_DEFECT_ADR_EN_BIT 0x20000000
#define REG_AUTO_DEFECT_ADU_EN_BIT 0x10000000
#define REG_AUTO_DEFECT_ADD_EN_BIT 0x08000000
#define REG_AUTO_DEFECT_DEADCHECK_BIT 0x04000000
#define REG_AUTO_DEFECT_GCHECK_SEL_MASK 0x03000000
#define REG_AUTO_DEFECT_RBCHECK_SEL_MASK 0x00C00000
#define REG_AUTO_DEFECT_BRIGHTTHD_MASK 0x00380000
#define REG_AUTO_DEFECT_BLACKTHD_MASK 0x00070000
#define REG_AUTO_DEFECT_AE_INTERVAL_MASK 0x0000FF00
#define REG_AUTO_DEFECT_GCHECKTHD_MASK 0xFF000000
#define REG_AUTO_DEFECT_RBCHECKTHD_MASK 0x00FF0000
#define REG_AUTO_DEFECT_GCORRECTTHD_MASK 0x0000FF00
#define REG_AUTO_DEFECT_RBCORRECTTHD_MASK 0x000000FF
/* bit mapping of flash control register */
#define REG_FLASH_OUT_BIT 0x80000000
#define REG_FLASH_EN_BIT 0x10000000
#define REG_FLASH_STARTPNT_BIT 0x01000000
#define REG_FLASH_POL_BIT 0x00100000
#define REG_FLASH_LNUNIT_MASK 0x000F0000
#define REG_FLASH_LNUNIT_NO_MASK 0x0000FF00
#define REG_FLASH_FRAME_DELAY_MASK 0x00000003
/* bit mapping of CAM reset register */
#define REG_CAM_RESET_ISP_FRAME_COUNT_MASK 0x0000FF00
#define REG_CAM_RESET_ISP_RESET_BIT 0x00000001
/* bit mapping of TG status register */
#define REG_TG_STATUS_MASK 0x0000003F
#endif
#if (defined(MT6228)||defined(MT6229)||defined(MT6230))
/* bit mapping of imageproc hue register */
#define REG_IMGPROC_HUE_ENABLE_BIT 0x00010000
#define REG_IMGPROC_HUE_HUE11_MASK 0x0000FF00
#define REG_IMGPROC_HUE_HUE12_MASK 0x000000FF
#define REG_IMGPROC_HUE_HUE21_MASK 0xFF000000
#define REG_IMGPROC_HUE_HUE22_MASK 0x00FF0000
#endif
/* macros of TG phase counter register */
#define ENABLE_CAMERA_TG_PHASE_COUNTER REG_ISP_TG_PHASE_COUNTER |= REG_TGPC_PHASE_COUNTER_ENABLE_BIT;
#define DISABLE_CAMERA_TG_PHASE_COUNTER REG_ISP_TG_PHASE_COUNTER &= ~REG_TGPC_PHASE_COUNTER_ENABLE_BIT;
#define ENABLE_CAMERA_CLOCK_OUTPUT_TO_CMOS REG_ISP_TG_PHASE_COUNTER |= REG_TGPC_CLK_OUTPUT_ENABLE_BIT;
#define DISABLE_CAMERA_CLOCK_OUTPUT_TO_CMOS REG_ISP_TG_PHASE_COUNTER &= ~REG_TGPC_CLK_OUTPUT_ENABLE_BIT;
#define SET_CMOS_CLOCK_POLARITY_HIGH REG_ISP_TG_PHASE_COUNTER |= REG_TGPC_CLK_POLARITY_CTRL_BIT;
#define SET_CMOS_CLOCK_POLARITY_LOW REG_ISP_TG_PHASE_COUNTER &= ~REG_TGPC_CLK_POLARITY_CTRL_BIT;
#define SET_TG_OUTPUT_CLK_DIVIDER(n) REG_ISP_TG_PHASE_COUNTER &= ~REG_TGPC_CLK_OUTPUT_DIV_MASK; \
REG_ISP_TG_PHASE_COUNTER |= (n<<24);
#define SET_CMOS_RISING_EDGE(n) REG_ISP_TG_PHASE_COUNTER &= ~REG_TGPC_RISING_EDGE_CLK_CNT_MASK; \
REG_ISP_TG_PHASE_COUNTER |= (n<<20);
#define SET_CMOS_FALLING_EDGE(n) REG_ISP_TG_PHASE_COUNTER &= ~REG_TGPC_FALLING_EDGE_CLK_CNT_MASK; \
REG_ISP_TG_PHASE_COUNTER |= (n<<16);
#define SET_TG_PIXEL_CLK_DIVIDER(n) REG_ISP_TG_PHASE_COUNTER &= ~REG_TGPC_PIXEL_CLK_DIV_MASK; \
REG_ISP_TG_PHASE_COUNTER |= (n<<4);
#define SET_CMOS_DATA_LATCH(n) REG_ISP_TG_PHASE_COUNTER &= ~REG_TGPC_DATA_LATCH_POSITION_MASK;\
REG_ISP_TG_PHASE_COUNTER |= n;
#if (defined(MT6226)||defined(MT6226M)||defined(MT6227)||defined(MT6228)||defined(MT6229)||defined(MT6230))
#define ENABLE_CAMERA_SENSOR_HVALID_HREF REG_ISP_TG_PHASE_COUNTER |= REG_TGPC_HVALID_ENABLE_BIT;
#define DISABLE_CAMERA_SENSOR_HVALID_HREF REG_ISP_TG_PHASE_COUNTER &= ~REG_TGPC_HVALID_ENABLE_BIT;
#define ENABLE_CAMERA_SENSOR_CLKIN_MONITOR REG_ISP_TG_PHASE_COUNTER |= REG_TGPC_SENSOR_CLKIN_MONITOR_BIT;
#define DISABLE_CAMERA_SENSOR_CLKIN_MONITOR REG_ISP_TG_PHASE_COUNTER &= ~REG_TGPC_SENSOR_CLKIN_MONITOR_BIT;
#define ENABLE_CAMERA_PIXEL_CLK_INV REG_ISP_TG_PHASE_COUNTER |= REG_TGPC_PIXEL_CLK_INV_BIT;
#define DISABLE_CAMERA_PIXEL_CLK_INV REG_ISP_TG_PHASE_COUNTER &= ~REG_TGPC_PIXEL_CLK_INV_BIT;
#define ENABLE_CAMERA_PIXEL_CLKIN_ENABLE REG_ISP_TG_PHASE_COUNTER |= REG_TGPC_PIXEL_CLKIN_ENABLE_BIT;
#define DISABLE_CAMERA_PIXEL_CLKIN_ENABLE REG_ISP_TG_PHASE_COUNTER &= ~REG_TGPC_PIXEL_CLKIN_ENABLE_BIT;
#define ENABLE_CAMERA_TG_CLK_48M REG_ISP_TG_PHASE_COUNTER |= REG_TGPC_PIXEL_CLK_SELECT_BIT;
#define DISABLE_CAMERA_TG_CLK_48M REG_ISP_TG_PHASE_COUNTER &= ~REG_TGPC_PIXEL_CLK_SELECT_BIT;
#endif
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