isp_if.h

最新MTK手机软件源码

#define REG_TGPC_PHASE_COUNTER_ENABLE_BIT		0x80000000
#define REG_TGPC_CLK_OUTPUT_ENABLE_BIT			0x20000000
#define REG_TGPC_CLK_POLARITY_CTRL_BIT			0x10000000
#define REG_TGPC_CLK_OUTPUT_DIV_MASK			0x0F000000
#define REG_TGPC_RISING_EDGE_CLK_CNT_MASK		0x00F00000
#define REG_TGPC_FALLING_EDGE_CLK_CNT_MASK	0x000F0000
#if (defined(MT6226)||defined(MT6226M)||defined(MT6227)||defined(MT6228)||defined(MT6229)||defined(MT6230))
#define REG_TGPC_HVALID_ENABLE_BIT				0x00008000
#define REG_TGPC_SENSOR_CLKIN_MONITOR_BIT		0x00004000
#define REG_TGPC_PIXEL_CLK_INV_BIT				0x00002000
#define REG_TGPC_PIXEL_CLKIN_ENABLE_BIT		0x00001000
#define REG_TGPC_PIXEL_CLK_SELECT_BIT			0x00000100
#endif
#define REG_TGPC_PIXEL_CLK_DIV_MASK				0x000000F0
#define REG_TGPC_DATA_LATCH_POSITION_MASK		0x0000000F

/* bit mapping of Camera CMOS sensor size configuration register */
#define REG_CMOS_SENSOR_SIZE_WIDTH_MASK		0x0FFF0000
#define REG_CMOS_SENSOR_SIZE_HEIGHT_MASK		0x00000FFF

/* bit mapping of TG grab range start/end pixel configuration register */
#define REG_TG_GRAB_RANGE_START_PIXEL_MASK	0x0FFF0000
#define REG_TG_GRAB_RANGE_END_PIXEL_MASK		0x00000FFF

/* bit mapping of TG grab start/end line configuration register */
#define REG_TG_GRAB_RANGE_START_LINE_MASK		0x0FFF0000
#define REG_TG_GRAB_RANBE_END_LINE_MASK		0x00000FFF

/* bit mapping of CMOS sensor mode configuration register */
#define REG_CMOS_SENSOR_VSYNC_POLARITY_BIT	0x00000080
#define REG_CMOS_SENSOR_HSYNC_POLARITY_BIT	0x00000040
#define REG_CMOS_SENSOR_POWER_ON_BIT			0x00000020
#define REG_CMOS_SENSOR_RESET_BIT				0x00000010
#define REG_CMOS_SENSOR_AUTO_SYNC_ENABLE_BIT	0x00000008
#define REG_CMOS_SENSOR_ENABLE_BIT				0x00000001

/* bit mapping of component R, Gr, B, Gb offset adjustment register */
#define REG_COMP_R_OFFSET_ADJ_SIGN_BIT			0x80000000
#define REG_COMP_R_OFFSET_ADJ_MASK				0x7F000000
#define REG_COMP_GR_OFFSET_ADJ_SIGN_BIT		0x00800000
#define REG_COMP_GR_OFFSET_ADJ_MASK				0x007F0000
#define REG_COMP_B_OFFSET_ADJ_SIGN_BIT			0x00008000
#define REG_COMP_B_OFFSET_ADJ_MASK				0x00007F00
#define REG_COMP_GB_OFFSET_ADJ_SIGN_BIT		0x00000080
#define REG_COMP_GB_OFFSET_ADJ_MASK				0x0000007F

/* bit mapping of camera view finder mode control register */
#if (defined(MT6226)||defined(MT6226M)||defined(MT6227)||defined(MT6228)||defined(MT6229)||defined(MT6230))
#define REG_VIEW_FINDER_MODE_SP_DELAY_MASK		0x00000700	
#endif
#define REG_VIEW_FINDER_MODE_DATA_ENABLE_BIT		0x00000040
#define REG_VIEW_FINDER_MODE_CAPTURE_MODE_BIT	0x00000080
#define REG_VIEW_FINDER_MODE_FRAME_RATE_MASK		0x00000007

/* bit mapping of Camera module interrupt enable register */
#if (defined(MT6226)||defined(MT6226M)||defined(MT6227)||defined(MT6229)||defined(MT6230))
#define REG_CAMERA_INT_VD_DONE_ENABLE_BIT				0x80000080
#define REG_CAMERA_INT_FLASH_SEL_ENABLE_BIT			0x80000000
#define REG_CAMERA_INT_FLASH_LINENO_MASK				0x0FFF0000
#define REG_CAMERA_INT_AVSYNC_ENABLE_BIT				0x00000100
#define REG_CAMERA_INT_FLASH_DONE_ENABLE_BIT			0x00000080
#elif (defined(MT6228))
#define REG_CAMERA_INT_VD_DONE_ENABLE_BIT				0x01000080
#define REG_CAMERA_INT_VSYNC_ENABLE_BIT				0x01000000
#define REG_CAMERA_INT_TG_LINENO_MASK					0x00FF0000
#define REG_CAMERA_INT_TG_DONE_ENABLE_BIT				0x00000080
#endif
#if (defined(MT6226)||defined(MT6226M)||defined(MT6227)||defined(MT6228)||defined(MT6229)||defined(MT6230))
#define REG_CAMERA_INT_ATF_DONE_ENABLE_BIT			0x00000040
#define REG_CAMERA_INT_AE_DONE_ENABLE_BIT				0x00000020
#define REG_CAMERA_INT_ISP_DONE_ENABLE_BIT			0x00000010
#endif
#define REG_CAMERA_INT_IDLE_ENABLE_BIT					0x00000008
#define REG_CAMERA_INT_GMC_OVERRUN_ENABLE_BIT		0x00000004
#define REG_CAMERA_INT_RESIZER_OVERRUN_ENABLE_BIT	0x00000002
#define REG_CAMERA_INT_FRAME_READY_ENABLE_BIT   	0x00000001

/* bit mapping of Camera module interrupt status register */
#if (defined(MT6226)||defined(MT6226M)||defined(MT6227)||defined(MT6228)||defined(MT6229)||defined(MT6230))
#define REG_CAMERA_INT_AE_DONE_STATUS_BIT				0x00000020
#define REG_CAMERA_INT_ISP_DONE_STATUS_BIT			0x00000010
#endif
#define REG_CAMERA_INT_IDLE_STATUS_BIT					0x00000008
#define REG_CAMERA_INT_GMC_OVERRUN_STATUS_BIT		0x00000004
#define REG_CAMERA_INT_RESIZER_OVERRUN_STATUS_BIT	0x00000002
#define REG_CAMERA_INT_FRAME_READY_STATUS_BIT   	0x00000001

#if (defined(MT6226)||defined(MT6226M)||defined(MT6227)||defined(MT6228)||defined(MT6229)||defined(MT6230))
/* bit mapping of Camera path config register */
#define REG_CAMERA_PATH_CNTON_BIT						0x80000000
#define REG_CAMERA_PATH_CNTMODE_MASK					0x60000000
#if (defined(MT6228))
#define REG_CAMERA_PATH_WRITE_LEVEL_MASK				0x1F000000
#else
#define REG_CAMERA_PATH_WRITE_LEVEL_MASK				0x1E000000
#define REG_CAMERA_PATH_BAYER10_OUT_BIT				    0x01000000
#endif
#define REG_CAMERA_PATH_REZ_DISCONN_BIT				0x00800000
#define REG_CAMERA_PATH_REZ_LPF_OFF_BIT				0x00400000
#define REG_CAMERA_PATH_OUTPATH_TYPE_MASK				0x00300000
#define REG_CAMERA_PATH_BURSTW_TYPE_MASK				0x000E0000
#define REG_CAMERA_PATH_OUTPATH_EN_BIT					0x00010000
#define REG_CAMERA_PATH_INORDER_SEL_MASK			0x00003000
#define REG_CAMERA_PATH_INDATA_FORMAT_MASK			0x00000800
#define REG_CAMERA_PATH_INTYPE_SEL_MASK				0x00000700
#define REG_CAMERA_PATH_INPATH_RATE_MASK				0x000000F0
#define REG_CAMERA_PATH_INPATH_THROTTLE_BIT			0x00000002
#define REG_CAMERA_PATH_INPATH_SEL_BIT					0x00000001
#endif

/* bit mapping of preprocessing control register 1 */
#define REG_PREPROCESS1_GAIN_COMPENSATION_MASK	0xFF000000
#define REG_PREPROCESS1_PIXEL_LIMIT_MASK			0x00FF0000
#define REG_PREPROCESS1_BYPASS_PREGAIN_BIT		0x00008000
#define REG_PREPROCESS1_LID_POLARITY_BIT			0x00002000
#define REG_PREPROCESS1_PID_POLARITY_BIT			0x00001000
#define REG_PREPROCESS1_PREGAIN_INT_PART_MASK	0x00000300
#define REG_PREPROCESS1_PREGAIN_FRAC_PART_MASK	0x000000FF

/* bit mapping of G and B component gain control register */
#define REG_COMP_B_GAIN_CTRL_MASK				0x01FF0000
#if (defined(MT6219))
#define REG_COMP_G_GAIN_CTRL_MASK				0x000001FF
#else
#define REG_COMP_GB_GAIN_CTRL_MASK				0x000001FF
#endif

/* bit mapping of R component gain control register */
#define REG_COMP_R_GAIN_CTRL_MASK				0x01FF0000
#if (defined(MT6226)||defined(MT6226M)||defined(MT6227)||defined(MT6228)||defined(MT6229)||defined(MT6230))
#define REG_COMP_GR_GAIN_CTRL_MASK				0x000001FF
#endif

/* bit mapping of histogram boundary control register */
#define REG_HISTORGRAM_BOUNDARY1_MASK			0xFF000000
#define REG_HISTORGRAM_BOUNDARY2_MASK			0x00FF0000
#define REG_HISTORGRAM_BOUNDARY3_MASK			0x0000FF00
#define REG_HISTORGRAM_BOUNDARY4_MASK			0x000000FF
#define REG_HISTORGRAM_BOUNDARY5_MASK			0xFF000000
#if (defined(MT6226)||defined(MT6226M)||defined(MT6227)||defined(MT6228)||defined(MT6229)||defined(MT6230))
#define REG_HISTORGRAM_BOUNDARY6_MASK			0xFF000000
#define REG_HISTORGRAM_BOUNDARY7_MASK			0x00FF0000
#define REG_HISTORGRAM_BOUNDARY8_MASK			0x0000FF00
#define REG_HISTORGRAM_BOUNDARY9_MASK			0x000000FF
#define REG_HISTORGRAM_BOUNDARYA_MASK			0xFF000000
#define REG_HISTORGRAM_BOUNDARYB_MASK			0x00FF0000
#define REG_HISTORGRAM_BOUNDARYC_MASK			0x0000FF00
#define REG_HISTORGRAM_BOUNDARYD_MASK			0x000000FF
#define REG_HISTORGRAM_BOUNDARYE_MASK			0xFF000000
#define REG_HISTORGRAM_BOUNDARYF_MASK			0x00FF0000
#endif

/* bit mapping of preprocessing control register 2 */
#define REG_PREPROCESS2_AE_AREA_ALL_ENABLE_BIT	0x00800000
#define ERG_PREPROCESS2_AE_COUNT_ENABLE_BIT		0x00400000
#define REG_PREPROCESS2_AE_PID_POLARITY_BIT		0x00200000
#define REG_PREPROCESS2_AE_GID_POLARITY_BIT		0x00100000
#define REG_PREPROCESS2_AE_COUNT_CLEAR_BIT		0x00080000
#define REG_PREPROCESS2_AE_GM_SEL_MASK				0x00060000
#define REG_PREPROCESS2_AE_PATH_SEL_BIT			0x00010000
#define REG_PREPROCESS2_ATF_EDGE_ENABLE_BIT		0x00008000
#define REG_PREPROCESS2_ATF_AREA_ALL_ENABLE_BIT	0x00004000
#define REG_PREPROCESS2_AWB_AREA_ALL_ENABLE_BIT	0x00000800
#define REG_PREPROCESS2_AE_GREEN_ONLY_BIT			0x00000200
#define REG_PREPROCESS2_RLEN_BIT						0x00000100
#define REG_PREPROCESS2_INTER_TOP_ENABLE_BIT		0x00000040	/* INTERPOLATION MODULE */

/* bit mapping of AE window 1~9 registers */
#define REG_AE_WINDOW_LEFT_MASK				0xFF000000
#define REG_AE_WINDOW_RIGHT_MASK				0x00FF0000
#define REG_AE_WINDOW_TOP_MASK				0x0000FF00
#define REG_AE_WINDOW_BOTTOM_MASK			0x000000FF

/* bit mapping of AWB window register */
#define REG_EDGE_V_CTRL_HPEN_BIT				0x80000000
#define ERG_EDGE_V_CTRL_E_TH1_V_MASK		0x7F000000
#define REG_EDGE_V_CTRL_HALF_V_MASK			0x003F0000
#define REG_EDGE_V_CTRL_SUP_V_MASK			0x0000C000
#define REG_EDGE_V_CTRL_SDN_V_MASK			0x00003000
#define REG_EDGE_V_CTRL_E_TH3_V_MASK		0X000000FF

/* bit mapping of Color processing stage control register 1 */
#define REG_CPS1_BYPASS_INTERPOLATION_BIT		0x00000080
#define ERG_CPS1_NONLINEAR_MODE_ENABLE_BIT	0x00000008
#define REG_CPS1_LINE_EDGE_ENABLE_BIT			0x00000002
#define REG_CPS1_LINE_JUDGE_ENABLE_BIT			0x00000001

/* bit mapping of interpolation register*/
#define REG_INTERPOLATION1_THRESHOLD_V_MASK		0x3F000000
#define REG_INTERPOLATION1_THRESHOLD_SM_MASK		0x001F0000
#define REG_INTERPOLATION1_THRESHOLD_DHV_MASK	0x00003F00
#define REG_INTERPOLATION1_THRESHOLD_RT_MASK		0x0000001F
#define REG_INTERPOLATION2_THRESHOLD_LEDGE_MASK	0x0000007F

/* bit mapping of Edge core register */
#define REG_EDGE_CORE_COREH_MASK				0x7F000000
#define REG_EDGE_CORE_EMBOSS1_BIT			0x00800000
#define REG_EDGE_CORE_EMBOSS2_BIT			0x00400000
#define REG_EDGE_CORE_COREH2_MASK			0x003F0000
#define REG_EDGE_CORE_COREV_MASK				0x00000F00
#define REG_EDGE_CORE_TOP_SLOPE_BIT			0x00000080
#define REG_EDGE_CORE_CORE_CON_MASK			0x0000007F

/* bit mapping of edge gain register 1*/
#define REG_EDGE_GAIN1_SPECIGAIN_MASK		0xC0000000
#define REG_EDGE_GAIN1_SPECIPONLY_MASK		0x30000000
#define REG_EDGE_GAIN1_EGAIN_H_MASK			0x0F000000
#define REG_EDGE_GAIN1_EGAIN_H2_MASK		0x000F0000
#define REG_EDGE_GAIN1_EGAIN_VB_MASK		0x00000F00
#define REG_EDGE_GAIN1_OILEN_BIT				0x00000080
#define REG_EDGE_GAIN1_KNEESEL_MASK			0x00000030
#define REG_EDGE_GAIN1_EGAINLINE_MASK		0x0000000F

/* bit mapping of edge gain register 2*/
#define REG_EDGE_GAIN2_SPECIABS_BIT			0x00000080
#define REG_EDGE_GAIN2_SPECIINV_BIT			0x00000040
#define REG_EDGE_GAIN2_EGAIN_HC_MASK		0x0000001F
#if (defined(MT6226)||defined(MT6226M)||defined(MT6227)||defined(MT6229)||defined(MT6230))
#define REG_EDGE_GAIN2_EGAIN_VC_MASK		0x001F0000
#define REG_EDGE_GAIN2_EGAIN_VA_MASK		0x0F000000
#endif

/* bit mapping of Edge threshold register */
#define REG_EDGE_THRESHOLD_ETH3_MASK				0xFF000000
#define REG_EDGE_THRESHOLD_ETH_CON_MASK			0x00FF0000
#define REG_EDGE_THRESHOLD_ONLYC_BIT				0x00008000
#define REG_EDGE_THRESHOLD_THRE_EDGE_SUP_MASK	0x00007F00
#define REG_EDGE_THRESHOLD_THRL_EDGE_SUP_MASK	0x0000007F

/* bit mapping of Edge vertical control register */
#define REG_EDGE_VERTICAL_HPEN_BIT				0x80000000
#define REG_EDGE_VERTICAL_E_TH1_V_MASK			0x7F000000
#define REG_EDGE_VERTICAL_HALF_V_MASK			0x003F0000
#define REG_EDGE_VERTICAL_SUP_V_MASK			0x00000C00
#define REG_EDGE_VERTICAL_SDN_V_MASK			0x00000300
#define REG_EDGE_VERTICAL_E_TH3_V_MASK			0x000000FF

/* bit mapping of Axis RGB gain register */
#define REG_AXIS_RGB_GAIN_R_GAIN_MASK			0x003F0000
#define REG_AXIS_RGB_GAIN_G_GAIN_MASK			0x00003F00
#define REG_AXIS_RGB_GAIN_B_GAIN_MASK			0x0000003F

/* bit mapping of OPD configuration register */
#define REG_OPD_CONFIG_OPD_ENABLE_BIT			0x80000000
#define REG_OPD_CONFIG_OPD_CLEAR_BIT			0x40000000
#define REG_OPD_CONFIG_COLOR_SUP_SEL_MASK		0x07000000
#define REG_OPD_CONFIG_U_GAIN_MASK				0x001F0000
#define REG_OPD_CONFIG_V_GAIN_MASK				0x00001F00
#define REG_OPD_CONFIG_Y_LIMIT_MASK				0x0000000F

/* bit mapping of OPD configuration parameter register */
#define REG_OPD_CONFIG_PARA_S_RB_P_MASK		0x7F000000
#define REG_OPD_CONFIG_PARA_S_RB_N_MASK		0x007F0000
#define REG_OPD_CONFIG_PARA_S_MG_P_MASK		0x00007F00
#define REG_OPD_CONFIG_PARA_S_MG_N_MASK		0x0000007F

/* bit mapping of color matrix 1~3 registers */
#define REG_COLOR_MATRIX_M1_MASK				0x00FF0000
#define REG_COLOR_MATRIX_M2_MASK				0x0000FF00
#define REG_COLOR_MATRIX_M3_MASK				0x000000FF

/* bit mapping of color matrix gain registers */
#define REG_COLOR_MATRIX_R_GAIN_MASK			0x003F0000
#define REG_COLOR_MATRIX_G_GAIN_MASK			0x00003F00
#define REG_COLOR_MATRIX_B_GAIN_MASK			0x0000003F

/* bit mapping of Color processing stage control register 1 */
#define REG_CPS2_BYPASS_GAMMA_BIT				0x00000080
#define REG_CPS2_RGB_EDGE_ENABLE_BIT			0x00000040
#define REG_CPS2_Y_EDGE_ENABLE_BIT				0x00000020
#define REG_CPS2_OPDGB_IVT_BIT					0x00000010
#define REG_CPS2_Y_EDGE_GAIN_MASK				0x0000000F

/* bit mapping of AWB RGB gain register */
#define REG_AWB_RGB_GAIN_R_GAIN_MASK			0x00FF0000
#define REG_AWB_RGB_GAIN_G_GAIN_MASK			0x0000FF00
#define REG_AWB_RGB_GAIN_B_GAIN_MASK			0x000000FF

/* bit mapping of Gamma RGB flare register */
#define REG_GAMMA_RGB_FLARE_SIGN_R_BIT			0x00800000
#define REG_GAMMA_RGB_FLARE_FLARE_R_MASK		0x003F0000
#define REG_GAMMA_RGB_FLARE_SIGN_G_BIT			0x00008000
#define REG_GAMMA_RGB_FLARE_FLARE_G_MASK		0x00003F00
#define REG_GAMMA_RGB_FLARE_SIGN_B_BIT			0x00000080
#define REG_GAMMA_RGB_FLARE_FLARE_B_MASK		0x0000003F

/* bit mapping of Y channel configuration register */
#define REG_Y_CH_CONFIG_CONTRAST_GAIN_MASK	0x007F0000
#define REG_Y_CH_ONFIG_BRIGHT_SIGN_BIT			0x00008000
#define REG_Y_CH_CONFIG_BRIGHT_OFFSET_MASK	0x00007F00
#if (defined(MT6226)||defined(MT6226M)||defined(MT6227)||defined(MT6228)||defined(MT6229)||defined(MT6230))
#define REG_VSUP_ENABLE_MASK						0x00000080
#define REG_UV_CH_LOW_PASS_ENABLE_MASK			0x00000020
#endif
#define REG_Y_CH_CONFIG_CSUP_EDGE_GAIN_MASK	0x0000001F

/* bit mapping of UV channel configuration register */
#define REG_UV_CH_CONFIG_U11_MASK				0xFF000000
#define REG_UV_CH_CONFIG_V11_MASK				0x00FF0000
#define REG_UV_CH_CONFIG_U_OFFSET_MASK			0x0000FF00
#define REG_UV_CH_CONFIG_V_OFFSET_MASK			0x000000FF

/* bit mapping of space convert YUV register 1~2 */
#define REG_SPACE_CVT_YUV_Y_GAIN_MASK			0x00FF0000