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📄 resizer.c

📁 最新MTK手机软件源码
💻 C
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	reg = (kal_uint16)(src_h%tar_h);
	if(reg > RESZ_VRES1_MAX)
		return RESZ_ERR_INVALID_SIZE;
//	DRV_WriteReg32(RESZ_VRES1, reg);
	DRV_WriteReg32(RESZ_VRES1, 0);

	return NO_ERROR;
}

/*
* FUNCTION
*	   RESZ_SetSize2
*
* DESCRIPTION
*   	setting the source width and height and target ones for twice resizing
*
* CALLS
*
* PARAMETERS
*	   src_w: width of source image
*	   src_h: height of source image
*	   tar_w: width of target image
*	   tar_h: height of target image
*		run: src indicate first or second run(0: first, 1: sencond)
*
* RETURNS
*	   None
*
* GLOBALS AFFECTED
*     None
*/
kal_int32 API RESZ_SetSize2(kal_uint32 src_w, kal_uint32 src_h, kal_uint32 tar_w, kal_uint32 tar_h, MMDI_SCENERIO_ID owner)
{
	kal_uint32 reg;

	ASSERT(resz_dcb.state != RESZ_BUSY);

	if( (src_w > 2047)||(src_w > 2047)||(src_w > 2047)||(src_w > 2047))
		return RESZ_ERR_INVALID_SIZE;

	reg = ((src_h<<16)|src_w);
	DRV_WriteReg32(RESZ_SRCSZ2, reg);
	reg = ((tar_h<<16)|tar_w);
	DRV_WriteReg32(RESZ_TARSZ2, reg);

	// set ratios
	reg = (kal_uint32)((src_w<<RESZ_H_RATIO_SHIFT_BITS)/tar_w);
	DRV_WriteReg32(RESZ_HRATIO2, reg);
	reg = (kal_uint32)((src_h<<RESZ_V_RATIO_SHIFT_BITS)/tar_h);
	DRV_WriteReg32(RESZ_VRATIO2, reg);

	// set residual
	reg = (kal_uint16)(src_w%tar_w);
	if(reg > RESZ_HRES1_MAX)
		return RESZ_ERR_INVALID_SIZE;
//	DRV_WriteReg32(RESZ_HRES2, reg);
	DRV_WriteReg32(RESZ_HRES2, 0);
	reg = (kal_uint16)(src_h%tar_h);
	if(reg > RESZ_VRES1_MAX)
		return RESZ_ERR_INVALID_SIZE;
//	DRV_WriteReg32(RESZ_VRES2, reg);
	DRV_WriteReg32(RESZ_VRES2, 0);

	return NO_ERROR;
}

/*
* FUNCTION
*	   RESZ_Start
*
* DESCRIPTION
*   	Trigger the resizing process
*
* CALLS
*
* PARAMETERS
*
* RETURNS
*	   None
*
* GLOBALS AFFECTED
*     None
*/
kal_int32 API RESZ_Start(MMDI_SCENERIO_ID owner)
{
	ASSERT(owner == resz_dcb.owner);

	ASSERT(resz_dcb.state == RESZ_READY);
	resz_dcb.state = RESZ_BUSY;

	DRV_WriteReg32(RESZ_CON, 0);
	if(resz_dcb.cfg.pixel_sel)
		DRV_WriteReg32(RESZ_CON, RESZ_PXL_EN);
	else
		DRV_WriteReg32(RESZ_CON, RESZ_BLK_EN);

	return NO_ERROR;
}

/*
* FUNCTION
*	   RESZ_Stop
*
* DESCRIPTION
*   	stop the resizing process.
*
* CALLS
*
* PARAMETERS
*
* RETURNS
*	   None
*
* GLOBALS AFFECTED
*     None
*/
kal_int32 API RESZ_Stop(MMDI_SCENERIO_ID owner)
{
	ASSERT(owner == resz_dcb.owner);

	DRV_WriteReg32(RESZ_CON, RESZ_ALL_RST);
	resz_dcb.state = RESZ_READY;

	return NO_ERROR;
}

/*
* FUNCTION
*	   RESZ_Stop
*
* DESCRIPTION
*   	stop the resizing process.
*
* CALLS
*
* PARAMETERS
*
* RETURNS
*	   None
*
* GLOBALS AFFECTED
*     None
*/
kal_bool API RESZ_CheckBusy(void)
{
	kal_uint32 reg;

	reg = DRV_Reg32(RESZ_STA);

	if(reg != 0)
		return KAL_TRUE;

	return KAL_FALSE;
}
#elif (defined(MT6228)||defined(MT6229)||defined(MT6230))

void RESZ_DRZConfig(RESZ_DRZ_STRUCT *drz_struct)
{
   STOP_DRZ;
   if(drz_struct->image_src==RESZ_SOURCE_IBW3)
   {
	   SET_DRZ_SRC_IBW3_DMA;
	}   
	else if(drz_struct->image_src==RESZ_SOURCE_MPEG4_ENCODE_DMA)
	{
	   SET_DRZ_SRC_VIDEO_ENCODE_DMA;   
	}   
	else
	   ASSERT(0);
	if(drz_struct->auto_restart==KAL_TRUE)   
	{
	   ENABLE_DRZ_AUTO_RESTART;
   }
	else
	{
	   DISABLE_DRZ_AUTO_RESTART;
	}   
	if(drz_struct->int_en==KAL_TRUE)   
	{
	   ENABLE_DRZ_INT;
	}
	else
	{
	   DISABLE_DRZ_INT;
   }   
   
	REG_DRZ_SOURCE_IMAGE_SIZE=((drz_struct->src_height-1)<<16)|(drz_struct->src_width-1);
	REG_DRZ_TARGET_IMAGE_SIZE=((drz_struct->tar_height-1)<<16)|(drz_struct->tar_width-1);
	
	REG_DRZ_H_RATIO =((drz_struct->src_width/drz_struct->tar_width)<<16)|((drz_struct->src_width%drz_struct->tar_width));
	REG_DRZ_V_RATIO =((drz_struct->src_height/drz_struct->tar_height)<<16)|((drz_struct->src_height%drz_struct->tar_height));
	
	START_DRZ;
}   

void RESZ_CRZConfig(RESZ_CRZ_STRUCT *crz_struct)
{
   RESET_CRZ;
	REG_CRZ_CTRL=0;
	if(crz_struct->dedicate_memory==KAL_TRUE)
	{
	   SET_CRZ_DEDICATED_MEMORY;
	   REG_CRZ_WORK_MEM_ADDR=0x40000000;	/* dummy for hardware issue */
	}
	else
	{
	   SET_CRZ_SHARED_MEMORY;  
	   REG_CRZ_WORK_MEM_ADDR=crz_struct->work_mem_addr;
	}      
	
	SET_CRZ_PIXEL_BASED_IMAGE;
	
   if(crz_struct->continous==KAL_TRUE)
   {
	   SET_CRZ_CONT_RUN_MODE;
	}   
	else
	{
	   SET_CRZ_SINGLE_RUN_MODE;
   }   
   
   switch(crz_struct->image_src)
   {
      case RESZ_SOURCE_ISP:
         SET_CRZ_PIXEL_BASED_SRC(CRZ_CONFIG_PIXEL_SRC_CAMERA_ISP);
      break;
      case RESZ_SOURCE_MPEG4_ENCODE_DMA:
         SET_CRZ_PIXEL_BASED_SRC(CRZ_CONFIG_PIXEL_SRC_MPEG4_ENCODE_DMA);
      break;
      case RESZ_SOURCE_MPEG4_DECODE_DMA:
         SET_CRZ_PIXEL_BASED_SRC(CRZ_CONFIG_PIXEL_SRC_MPEG4_DECODE_DMA);
      break;
      case RESZ_SOURCE_IBW4:
         SET_CRZ_PIXEL_BASED_SRC(CRZ_CONFIG_PIXEL_SRC_IBW_DMA);
      break;
      case RESZ_SOURCE_IPP:
         SET_CRZ_PIXEL_BASED_SRC(CRZ_CONFIG_PIXEL_SRC_IPP);
      break;
      default:
         ASSERT(0);
      break;         	   
   }
   
   if(crz_struct->int_en==KAL_TRUE)
   {
	   ENABLE_CRZ_H_RESIZE_INT;
	   ENABLE_CRZ_V_RESIZE_INT;
	}
	else
	{
	   DISABLE_CRZ_H_RESIZE_INT;
	   DISABLE_CRZ_V_RESIZE_INT;
	}      
   
   SET_CRZ_SRC_SIZE(crz_struct->src_width, crz_struct->src_height);
	/* set target size as the multiples of overlay frame buffer */
	SET_CRZ_TARGET_SIZE(crz_struct->tar_width,crz_struct->tar_height);	
	
	if (crz_struct->src_width==crz_struct->tar_width)
		REG_CRZ_H_RATIO=1<<RESZ_H_RATIO_SHIFT_BITS;
	else
		REG_CRZ_H_RATIO=((1<<RESZ_H_RATIO_SHIFT_BITS)/crz_struct->tar_width)*crz_struct->src_width;
		
	if (crz_struct->src_height==crz_struct->tar_height)
		REG_CRZ_V_RATIO=(1<<RESZ_V_RATIO_SHIFT_BITS);
	else
		REG_CRZ_V_RATIO=((1<<RESZ_V_RATIO_SHIFT_BITS)/crz_struct->tar_height)*crz_struct->src_height;

	REG_CRZ_H_RESIDUAL=crz_struct->src_width%crz_struct->tar_width;
	REG_CRZ_V_RESIDUAL=crz_struct->src_height%crz_struct->tar_height;
	
	REG_CRZ_FINE_RESIZE_CFG=0;
	SET_CRZ_FINE_RESIZE_WORK_MEM_SIZE(crz_struct->work_mem_line);
	
	ENABLE_CRZ;         
}   

void RESZ_PRZConfig(RESZ_PRZ_STRUCT *prz_struct)
{         
   RESET_PRZ;   
   REG_PRZ_CONFIG=0;
   REG_PRZ_FINE_RESIZE_CFG=0;
   
   switch(prz_struct->image_src)
   {
      case RESZ_SOURCE_MPEG4_ENCODE_DMA:
          SET_PRZ_SRC(PRZ_CONFIG_PIXEL_SRC_MPEG4_ENCODE_DMA);
      break;
      case RESZ_SOURCE_MPEG4_DECODE_DMA:
         SET_PRZ_SRC(PRZ_CONFIG_PIXEL_SRC_MPEG4_DECODE_DMA);
      break;
      case RESZ_SOURCE_IBW4:
         SET_PRZ_SRC(PRZ_CONFIG_PIXEL_SRC_IBW4_DMA);
      break;
      case RESZ_SOURCE_IPP:
         SET_PRZ_SRC(PRZ_CONFIG_PIXEL_SRC_IPP);
      break;
      case RESZ_SOURCE_JPEG_DECODER:
         SET_PRZ_SRC(PRZ_CONFIG_PIXEL_SRC_JPEG_DECODER);
      break;      
      default:
         ASSERT(0);
      break;   
   }
   if(prz_struct->dedicate_memory==KAL_TRUE)
   {
      SET_PRZ_DEDICATED_MEMORY;
      REG_PRZ_WORK_MEM_ADDR=0x40000000;
   }
   else
   {
      SET_PRZ_SHARED_MEMORY;
      REG_PRZ_WORK_MEM_ADDR=prz_struct->work_mem_addr;
   }   
   SET_PRZ_FINE_RESIZE_WORK_MEM_SIZE(prz_struct->work_mem_line);
   if(prz_struct->continous==KAL_TRUE)
   {
      SET_PRZ_CONT_MODE;
   }      
   else
   {
      SET_PRZ_SINGLE_MODE;
   }   
   if(prz_struct->int_en==KAL_TRUE)
   {
      
   }      
   else
   {
      
   }   
   if(prz_struct->output_2_IPP==KAL_TRUE)
   {
      SET_PRZ_FINE_RESIZE_OUTPUT_IPP;
   }
   if(prz_struct->coarse_en==KAL_TRUE)
   {
      SET_PRZ_BLOCK_MODE;
      SET_PRZ_BLOCK_CS_FACTOR(prz_struct->coarse_ratio);
      SET_PRZ_BLOCK_CS_Y_H_FACTOR(prz_struct->y_h_factor);
      SET_PRZ_BLOCK_CS_Y_V_FACTOR(prz_struct->y_v_factor);
      SET_PRZ_BLOCK_CS_U_H_FACTOR(prz_struct->u_h_factor);
		SET_PRZ_BLOCK_CS_U_V_FACTOR(prz_struct->u_v_factor);
		SET_PRZ_BLOCK_CS_V_H_FACTOR(prz_struct->v_h_factor);
		SET_PRZ_BLOCK_CS_V_V_FACTOR(prz_struct->v_v_factor);
		REG_PRZ_Y_LINE_BUFFER_ADDR=(kal_uint32)prz_struct->y_line_buff_addr;
		REG_PRZ_U_LINE_BUFFER_ADDR=(kal_uint32)prz_struct->u_line_buff_addr;
		REG_PRZ_V_LINE_BUFFER_ADDR=(kal_uint32)prz_struct->v_line_buff_addr;
		SET_PRZ_FINE_RESIZE_LINE_BUFFER(prz_struct->y_line_buff_size);
   }
   else   
   {
      SET_PRZ_PIXEL_MODE;
   }   
      
   SET_PRZ_SRC_SIZE(prz_struct->src_width,prz_struct->src_height);
	SET_PRZ_TARGET_SIZE(prz_struct->tar_width,prz_struct->tar_height);
	
	if (prz_struct->src_width==prz_struct->tar_width)
		REG_PRZ_H_RATIO=1<<RESZ_H_RATIO_SHIFT_BITS;
	else
		REG_PRZ_H_RATIO=((1<<RESZ_H_RATIO_SHIFT_BITS)/prz_struct->tar_width)*prz_struct->src_width;
		
	if (prz_struct->src_height==prz_struct->tar_height)
		REG_PRZ_V_RATIO=(1<<RESZ_V_RATIO_SHIFT_BITS);
	else
		REG_PRZ_V_RATIO=((1<<RESZ_V_RATIO_SHIFT_BITS)/prz_struct->tar_height)*prz_struct->src_height;

	REG_PRZ_H_RESIDUAL=prz_struct->src_width%prz_struct->tar_width;
	REG_PRZ_V_RESIDUAL=prz_struct->src_height%prz_struct->tar_height;                                              
   
   /* HW issue of PRZ src switch==>reset again */
	RESET_PRZ;
	if(prz_struct->coarse_en==KAL_TRUE)
	{
	   ENABLE_PRZ;   
	}
	else
	{
	   ENABLE_PRZ_H_LINE;
	   ENABLE_PRZ_V_LINE;      
	}      
}  
 
#endif   /* MT6219 */
#endif

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