📄 resizer.h
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#define ENABLE_PRZ_V_LINE REG_PRZ_CTRL |= PRZ_CTRL_V_FINE_RESIZE_ENABLE_BIT;
#define DISABLE_PRZ_V_LINE REG_PRZ_CTRL &= ~PRZ_CTRL_V_FINE_RESIZE_ENABLE_BIT;
#define ENABLE_PRZ REG_PRZ_CTRL = PRZ_CTRL_ENABLE_MASK;
/* Macros of PRZ status register */
#define IS_BLOCK_CS_BUSY (REG_PRZ_STATUS & PRZ_CTRL_BLOCK_CS_BUSY_BIT)
#define IS_PRZ_H_FINE_RESIZE_BUSY (REG_PRZ_STATUS & PRZ_CTRL_H_FINE_RESIZE_BUSY_BIT)
#define IS_PRZ_V_FINE_RESIZE_BUSY (REG_PRZ_STATUS & PRZ_CTRL_V_FINE_RESIZE_BUSY_BIT)
/* Macros of PRZ source image size register */
#define SET_PRZ_SRC_SIZE(width, height) REG_PRZ_SOURCE_IMAGE_SIZE=(width|(height<<16));
/* Macros of PRZ target image size register */
#define SET_PRZ_TARGET_SIZE(width, height) REG_PRZ_TARGET_IMAGE_SIZE=(width|(height<<16));
/* Macros of resizer block coarse shrinking config register */
#define SET_PRZ_BLOCK_CS_V_V_FACTOR(factor) REG_PRZ_BLOCK_CS_CFG &= ~PRZ_BLOCk_CS_CFG_V_V_SAMPLE_FACTOR_MASK;\
REG_PRZ_BLOCK_CS_CFG |= ((factor>>1)<<14);
#define SET_PRZ_BLOCK_CS_V_H_FACTOR(factor) REG_PRZ_BLOCK_CS_CFG &= ~PRZ_BLOCk_CS_CFG_V_H_SAMPLE_FACTOR_MASK;\
REG_PRZ_BLOCK_CS_CFG |= ((factor>>1)<<12);
#define SET_PRZ_BLOCK_CS_U_V_FACTOR(factor) REG_PRZ_BLOCK_CS_CFG &= ~PRZ_BLOCk_CS_CFG_U_V_SAMPLE_FACTOR_MASK;\
REG_PRZ_BLOCK_CS_CFG |= ((factor>>1)<<10);
#define SET_PRZ_BLOCK_CS_U_H_FACTOR(factor) REG_PRZ_BLOCK_CS_CFG &= ~PRZ_BLOCk_CS_CFG_U_H_SAMPLE_FACTOR_MASK;\
REG_PRZ_BLOCK_CS_CFG |= ((factor>>1)<<8);
#define SET_PRZ_BLOCK_CS_Y_V_FACTOR(factor) REG_PRZ_BLOCK_CS_CFG &= ~PRZ_BLOCk_CS_CFG_Y_V_SAMPLE_FACTOR_MASK;\
REG_PRZ_BLOCK_CS_CFG |= ((factor>>1)<<6);
#define SET_PRZ_BLOCK_CS_Y_H_FACTOR(factor) REG_PRZ_BLOCK_CS_CFG &= ~PRZ_BLOCk_CS_CFG_Y_H_SAMPLE_FACTOR_MASK;\
REG_PRZ_BLOCK_CS_CFG |= ((factor>>1)<<4);
#define SET_PRZ_BLOCK_CS_FACTOR(factor) REG_PRZ_BLOCK_CS_CFG &= ~PRZ_BLOCk_CS_CFG_CS_FACTOR_MASK;\
REG_PRZ_BLOCK_CS_CFG |= factor;
/* macros of PRZ fine resizer config register */
#define SET_PRZ_FINE_RESIZE_WORK_MEM_SIZE(line) REG_PRZ_FINE_RESIZE_CFG &= ~PRZ_FINE_RESIZE_WORK_MEM_SIZE_MASK;\
REG_PRZ_FINE_RESIZE_CFG |= (line<<16);
#define SET_PRZ_FINE_RESIZE_OUTPUT_IPP REG_PRZ_FINE_RESIZE_CFG |= PRZ_FINE_RESIZE_OUTPUT_SEL_BIT;
#define SET_PRZ_FINE_RESIZE_OUTPUT_IMG_DMA REG_PRZ_FINE_RESIZE_CFG &= ~PRZ_FINE_RESIZE_OUTPUT_SEL_BIT;
#define ENABLE_PRZ_H_RESIZE_INT REG_PRZ_FINE_RESIZE_CFG |= PRZ_H_FINE_RESIZE_INT;
#define DISABLE_PRZ_H_RESIZE_INT REG_PRZ_FINE_RESIZE_CFG &= ~PRZ_H_FINE_RESIZE_INT;
#define ENABLE_PRZ_V_RESIZE_INT REG_PRZ_FINE_RESIZE_CFG |= PRZ_V_FINE_RESIZE_INT;
#define DISABLE_PRZ_V_RESIZE_INT REG_PRZ_FINE_RESIZE_CFG &= ~PRZ_V_FINE_RESIZE_INT;
/* macros of PRZ line buffer size register */
#define SET_PRZ_FINE_RESIZE_LINE_BUFFER(n) REG_PRZ_LINE_BUFFER_SIZE = n;
/* CRZ definition */
#define CRZ_CONFIG_REG (CRZ_base + 0x00)
#define CRZ_CTRL_REG (CRZ_base + 0x04)
#define CRZ_STATUS_REG (CRZ_base + 0x08)
#define CRZ_INT_STATUS_REG (CRZ_base + 0x0C)
#define CRZ_SOURCE_IMAGE_SIZE_REG (CRZ_base + 0x10)
#define CRZ_TARGET_IMAGE_SIZE_REG (CRZ_base + 0x14)
#define CRZ_H_RATIO_REG (CRZ_base + 0x18)
#define CRZ_V_RATIO_REG (CRZ_base + 0x1C)
#define CRZ_H_RESIDUAL_REG (CRZ_base + 0x20)
#define CRZ_V_RESIDUAL_REG (CRZ_base + 0x24)
#define CRZ_FINE_RESIZE_CFG_REG (CRZ_base + 0x40)
#define CRZ_WORK_MEM_ADDR_REG (CRZ_base + 0x5C)
#define REG_CRZ_CONFIG *((volatile unsigned int *) (CRZ_base + 0x00))
#define REG_CRZ_CTRL *((volatile unsigned int *) (CRZ_base + 0x04))
#define REG_CRZ_STATUS *((volatile unsigned int *) (CRZ_base + 0x08))
#define REG_CRZ_INT_STATUS *((volatile unsigned int *) (CRZ_base + 0x0C))
#define REG_CRZ_SOURCE_IMAGE_SIZE *((volatile unsigned int *) (CRZ_base + 0x10))
#define REG_CRZ_TARGET_IMAGE_SIZE *((volatile unsigned int *) (CRZ_base + 0x14))
#define REG_CRZ_H_RATIO *((volatile unsigned int *) (CRZ_base + 0x18))
#define REG_CRZ_V_RATIO *((volatile unsigned int *) (CRZ_base + 0x1C))
#define REG_CRZ_H_RESIDUAL *((volatile unsigned int *) (CRZ_base + 0x20))
#define REG_CRZ_V_RESIDUAL *((volatile unsigned int *) (CRZ_base + 0x24))
#define REG_CRZ_FINE_RESIZE_CFG *((volatile unsigned int *) (CRZ_base + 0x40))
#define REG_CRZ_WORK_MEM_ADDR *((volatile unsigned int *) (CRZ_base + 0x5C))
/* bit mapping of CRZ config register */
#define CRZ_CONFIG_LINE_BUF_SEL_BIT 0x00000080
#define CRZ_CONFIG_PIXEL_SRC_MASK 0x0000000F
#define CRZ_CONFIG_SRC_SEL_BIT 0x00000020
#define CRZ_CONFIG_CONT_RUN_BIT 0x00000010
#define CRZ_CONFIG_PIXEL_SRC_CAMERA_ISP 0
#define CRZ_CONFIG_PIXEL_SRC_MPEG4_ENCODE_DMA 1
#define CRZ_CONFIG_PIXEL_SRC_MPEG4_DECODE_DMA 2
#define CRZ_CONFIG_PIXEL_SRC_IBW_DMA 3
#define CRZ_CONFIG_PIXEL_SRC_IPP 6
/* bit mapping of CRZ control register */
#define CRZ_CTRL_RESET_MASK 0x00060000
#define CRZ_CTRL_ENABLE_MASK 0x00000006
#define CRZ_CTRL_H_FINE_RESIZE_ENABLE_BIT 0x00000002
#define CRZ_CTRL_V_FINE_RESIZE_ENABLE_BIT 0x00000004
#define CRZ_CTRL_H_FINE_RESIZE_RESET_BIT 0x00020000
#define CRZ_CTRL_V_FINE_RESIZE_RESET_BIT 0x00040000
/* bit mapping of CRZ status register */
#define CRZ_CTRL_H_FINE_RESIZE_BUSY_BIT 0x00000002
#define CRZ_CTRL_V_FINE_RESIZE_BUSY_BIT 0x00000004
/* bit mapping of CRZ interrupt status register */
#define CRZ_CTRL_H_FINE_RESIZE_INT_BIT 0x00000002
#define CRZ_CTRL_V_FINE_RESIZE_INT_BIT 0x00000004
/* bit mapping of CRZ source and target size register */
#define CRZ_IMAGE_SIZE_WIDTH_MASK 0x0000FFFF
#define CRZ_IMAGE_SIZE_HEIGHT_MASK 0xFFFF0000
/* bit mapping of CRZ fine resize config register */
#define CRZ_FINE_RESIZE_WORK_MEM_SIZE_MASK 0xFFFF0000
#define CRZ_H_FINE_RESIZE_INT 0x00000010
#define CRZ_V_FINE_RESIZE_INT 0x00000020
/* macros of CRZ config register */
#define SET_CRZ_DEDICATED_MEMORY REG_CRZ_CONFIG |= CRZ_CONFIG_LINE_BUF_SEL_BIT;
#define SET_CRZ_SHARED_MEMORY REG_CRZ_CONFIG &= ~CRZ_CONFIG_LINE_BUF_SEL_BIT;
#define SET_CRZ_PIXEL_BASED_IMAGE REG_CRZ_CONFIG |= CRZ_CONFIG_SRC_SEL_BIT;
#define SET_CRZ_BLOCK_BASED_IMAGE REG_CRZ_CONFIG &= ~CRZ_CONFIG_SRC_SEL_BIT;
#define SET_CRZ_CONT_RUN_MODE REG_CRZ_CONFIG |= CRZ_CONFIG_CONT_RUN_BIT;
#define SET_CRZ_SINGLE_RUN_MODE REG_CRZ_CONFIG &= ~CRZ_CONFIG_CONT_RUN_BIT;
#define SET_CRZ_PIXEL_BASED_SRC(n) REG_CRZ_CONFIG &= ~CRZ_CONFIG_PIXEL_SRC_MASK;\
REG_CRZ_CONFIG |= n;
/* marcos of CRZ control register */
#define RESET_CRZ REG_CRZ_CTRL=CRZ_CTRL_RESET_MASK;\
REG_CRZ_CTRL=0;
#define SET_CRZ_H_FINE_RESIZE_RESET REG_CRZ_CTRL |= CRZ_CTRL_H_FINE_RESIZE_RESET_BIT;
#define CLEAR_CRZ_H_FINE_RESIZE_RESET REG_CRZ_CTRL &= ~CRZ_CTRL_H_FINE_RESIZE_RESET_BIT;
#define SET_CRZ_V_FINE_RESIZE_RESET REG_CRZ_CTRL |= CRZ_CTRL_V_FINE_RESIZE_RESET_BIT;
#define CLEAR_CRZ_V_FINE_RESIZE_RESET REG_CRZ_CTRL &= ~CRZ_CTRL_V_FINE_RESIZE_RESET_BIT;
#define ENABLE_CRZ_H_LINE REG_CRZ_CTRL |= CRZ_CTRL_H_FINE_RESIZE_ENABLE_BIT;
#define DISABLE_CRZ_H_LINE REG_CRZ_CTRL &= ~CRZ_CTRL_H_FINE_RESIZE_ENABLE_BIT;
#define ENABLE_CRZ_V_LINE REG_CRZ_CTRL |= CRZ_CTRL_V_FINE_RESIZE_ENABLE_BIT;
#define DISABLE_CRZ_V_LINE REG_CRZ_CTRL &= ~CRZ_CTRL_V_FINE_RESIZE_ENABLE_BIT;
#define ENABLE_CRZ REG_CRZ_CTRL = CRZ_CTRL_ENABLE_MASK;
/* Macros of CRZ status register */
#define IS_CRZ_H_FINE_RESIZE_BUSY (REG_CRZ_STATUS & CRZ_CTRL_H_FINE_RESIZE_BUSY_BIT)
#define IS_CRZ_V_FINE_RESIZE_BUSY (REG_CRZ_STATUS & CRZ_CTRL_V_FINE_RESIZE_BUSY_BIT)
/* Macros of CRZ source image size register */
#define SET_CRZ_SRC_SIZE(width, height) REG_CRZ_SOURCE_IMAGE_SIZE=(width|(height<<16));
/* Macros of CRZ target image size register */
#define SET_CRZ_TARGET_SIZE(width, height) REG_CRZ_TARGET_IMAGE_SIZE=(width|(height<<16));
/* macros of CRZ fine resizer config register */
#define SET_CRZ_FINE_RESIZE_WORK_MEM_SIZE(line) REG_CRZ_FINE_RESIZE_CFG &= ~CRZ_FINE_RESIZE_WORK_MEM_SIZE_MASK;\
REG_CRZ_FINE_RESIZE_CFG |= (line<<16);
#define ENABLE_CRZ_H_RESIZE_INT REG_CRZ_FINE_RESIZE_CFG |= CRZ_H_FINE_RESIZE_INT;
#define DISABLE_CRZ_H_RESIZE_INT REG_CRZ_FINE_RESIZE_CFG &= ~CRZ_H_FINE_RESIZE_INT;
#define ENABLE_CRZ_V_RESIZE_INT REG_CRZ_FINE_RESIZE_CFG |= CRZ_V_FINE_RESIZE_INT;
#define DISABLE_CRZ_V_RESIZE_INT REG_CRZ_FINE_RESIZE_CFG &= ~CRZ_V_FINE_RESIZE_INT;
/* DRZ definition */
#define DRZ_START_REG (DRZ_base + 0x00)
#define DRZ_CONFIG_REG (DRZ_base + 0x04)
#define DRZ_STATUS_REG (DRZ_base + 0x08)
#define DRZ_INT_ACK_REG (DRZ_base + 0x0C)
#define DRZ_SOURCE_IMAGE_SIZE_REG (DRZ_base + 0x10)
#define DRZ_TARGET_IMAGE_SIZE_REG (DRZ_base + 0x14)
#define DRZ_H_RATIO_REG (DRZ_base + 0x20)
#define DRZ_V_RATIO_REG (DRZ_base + 0x24)
#define REG_DRZ_START *((volatile unsigned int *) (DRZ_base + 0x00))
#define REG_DRZ_CONFIG *((volatile unsigned int *) (DRZ_base + 0x04))
#define REG_DRZ_STATUS *((volatile unsigned int *) (DRZ_base + 0x08))
#define REG_DRZ_INT_ACK *((volatile unsigned int *) (DRZ_base + 0x0C))
#define REG_DRZ_SOURCE_IMAGE_SIZE *((volatile unsigned int *) (DRZ_base + 0x10))
#define REG_DRZ_TARGET_IMAGE_SIZE *((volatile unsigned int *) (DRZ_base + 0x14))
#define REG_DRZ_H_RATIO *((volatile unsigned int *) (DRZ_base + 0x20))
#define REG_DRZ_V_RATIO *((volatile unsigned int *) (DRZ_base + 0x24))
/* bit mapping of DRZ configuration register */
#define DRZ_CONFIG_PIXEL_SEL_BIT 0x00000010
#define DRZ_CONFIG_AUTO_RESTART_BIT 0x00000008
#define DRZ_CONFIG_INT_ENABLE_BIT 0x00000001
/* bit mapping of DRZ status register */
#define DRZ_STATUS_BUSY_BIT 0x00010000
#define DRZ_STATUS_INT_BIT 0x00000001
/* bit mapping of DRZ interrupt acknowledge register */
#define DRZ_INT_ACK_BIT 0x00000001
/* macros of DRZ start register */
#define START_DRZ REG_DRZ_START=1;
#define STOP_DRZ REG_DRZ_START=0;
/* macros of DRZ configuration register */
#define SET_DRZ_SRC_VIDEO_ENCODE_DMA REG_DRZ_CONFIG &= ~DRZ_CONFIG_PIXEL_SEL_BIT;
#define SET_DRZ_SRC_IBW3_DMA REG_DRZ_CONFIG |= DRZ_CONFIG_PIXEL_SEL_BIT;
#define ENABLE_DRZ_AUTO_RESTART REG_DRZ_CONFIG |= DRZ_CONFIG_AUTO_RESTART_BIT;
#define DISABLE_DRZ_AUTO_RESTART REG_DRZ_CONFIG &= ~DRZ_CONFIG_AUTO_RESTART_BIT;
#define ENABLE_DRZ_INT REG_DRZ_CONFIG |= DRZ_CONFIG_INT_ENABLE_BIT;
#define DISABLE_DRZ_INT REG_DRZ_CONFIG &= ~DRZ_CONFIG_INT_ENABLE_BIT;
/* macros of DRZ status register */
#define DRZ_IS_RUNNING (REG_DRZ_STATUS & DRZ_STATUS_BUSY_BIT)
/* macros of DRZ interrupt ACK register */
#define ACK_DRZ_INT REG_DRZ_INT_ACK=DRZ_INT_ACK_BIT;
/*Enum*/
typedef enum{
RESZ_SOURCE_MPEG4_ENCODE_DMA,
RESZ_SOURCE_MPEG4_DECODE_DMA,
RESZ_SOURCE_IBW3,
RESZ_SOURCE_IBW4,
RESZ_SOURCE_IPP,
RESZ_SOURCE_ISP,
RESZ_SOURCE_JPEG_DECODER
}RESZ_SOURCE_ENUM;
/*structure */
typedef struct{
RESZ_SOURCE_ENUM image_src;
kal_bool auto_restart;
kal_bool int_en;
kal_uint16 src_height;
kal_uint16 src_width;
kal_uint16 tar_height;
kal_uint16 tar_width;
}RESZ_DRZ_STRUCT;
typedef struct{
RESZ_SOURCE_ENUM image_src;
kal_bool dedicate_memory;
kal_bool continous;
kal_bool int_en;
kal_uint16 src_height;
kal_uint16 src_width;
kal_uint16 tar_height;
kal_uint16 tar_width;
kal_uint16 work_mem_line;
kal_uint32 work_mem_addr;
}RESZ_CRZ_STRUCT;
typedef struct{
RESZ_SOURCE_ENUM image_src;
kal_bool dedicate_memory;
kal_bool continous;
kal_bool int_en;
kal_bool output_2_IPP;
kal_bool coarse_en;
kal_uint16 src_height;
kal_uint16 src_width;
kal_uint16 tar_height;
kal_uint16 tar_width;
kal_uint16 work_mem_line;
kal_uint32 work_mem_addr;
kal_uint32 y_line_buff_addr;
kal_uint32 u_line_buff_addr;
kal_uint32 v_line_buff_addr;
kal_uint32 y_line_buff_size;
kal_uint32 coarse_ratio;
kal_uint8 y_h_factor;
kal_uint8 y_v_factor;
kal_uint8 u_h_factor;
kal_uint8 u_v_factor;
kal_uint8 v_h_factor;
kal_uint8 v_v_factor;
}RESZ_PRZ_STRUCT;
extern void RESZ_CRZConfig(RESZ_CRZ_STRUCT *crz_struct);
extern void RESZ_PRZConfig(RESZ_PRZ_STRUCT *prz_struct);
extern void RESZ_DRZConfig(RESZ_DRZ_STRUCT *drz_struct);
#endif/*MT6228, MT6229, MT6230*/
#endif //RESIZER_H
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