📄 resizer.h
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}RESZ_VV_SAMPLING_FACTOR_ENUM;
// structures
typedef struct{
kal_uint32 src1 :4;// select pixel based image source(RESZ_PXL_SRC_ENUM)
kal_uint32 pcontinue :1;// if pixel based resizing continue(1: continue resizeing, 0: single resizing
kal_uint32 pixel_sel :1;// determine pixel-based or block based image(block mode imply jpeg decoder as source )
kal_uint32 run2 :1;// resize two times
kal_uint32 :1;// padding
kal_uint32 src2 :4;// select pixel based image source2
kal_uint32 :4;// padding
}RESZ_CFG_STRUCT;
typedef struct{
// sampling factors
kal_uint32 csf :2;// coarse shrink factor(RESZ_CS_FACTOR_ENUM)
kal_uint32 :2;
kal_uint32 hy :2;// Y horizontal sampling factor(RESZ_HY_SAMPLING_FACTOR_ENUM)
kal_uint32 vy :2;// Y vertical sampling factor(RESZ_VY_SAMPLING_FACTOR_ENUM)
kal_uint32 hu :2;// U horizontal sampling factor(RESZ_HU_SAMPLING_FACTOR_ENUM)
kal_uint32 vu :2;// U vertical sampling factor(RESZ_VU_SAMPLING_FACTOR_ENUM)
kal_uint32 hv :2;// V horizontal sampling factor(RESZ_HV_SAMPLING_FACTOR_ENUM)
kal_uint32 vv :2;// V vertical sampling factor(RESZ_VV_SAMPLING_FACTOR_ENUM)
// size of line bffer
kal_uint32 ylbsize:16;// Y component line buffer size
kal_uint32 ulbsize:16;// U component line buffer size
kal_uint32 vlbsize:16;// V component line buffer size
// size of working memory
kal_uint32 wmsize:16;
// base address of line buffers
kal_uint32 ylmbase:32;
kal_uint32 ulmbase:32;
kal_uint32 vlmbase:32;
// base address of working memory
kal_uint32 ywmbase:32;
kal_uint32 uwmbase:32;
kal_uint32 vwmbase:32;
}RESZ_BLK_CFG_STRUCT;
typedef struct{
kal_uint16 wmsize;
kal_uint32 wmbase;
}RESZ_PXL_CFG_STRUCT;
typedef struct{
MMDI_SCENERIO_ID owner;
RESZ_STATE_ENUM state;
RESZ_CFG_STRUCT cfg;
#if 0
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
#endif
}RESZ_DCB_STRUCT;
// macro
#define RESZ_BYPASS() DRV_Reg32(RESZ_BASE+0x90) |= 0x8000
#define RESZ_SET_WMBASE_PXL(a) DRV_WriteReg32(RESZ_PRWMBASE, (a))
#define RESZ_SET_WMBASE_BLK(y,u,v) \
{\
DRV_WriteReg32(RESZ_YWMBASE, y);\
DRV_WriteReg32(RESZ_UWMBASE, u);\
DRV_WriteReg32(RESZ_VWMBASE, v);\
}
#define RESZ_SET_LMBASE_BLK(y,u,v) \
{\
DRV_WriteReg32(RESZ_YLMBASE, y);\
DRV_WriteReg32(RESZ_ULMBASE, u);\
DRV_WriteReg32(RESZ_VLMBASE, v);\
}
#define RESZ_SET_LBSIZE_BLK(y,u,v) \
{\
DRV_WriteReg(RESZ_YLBSIZE, y);\
DRV_WriteReg(RESZ_ULBSIZE, u);\
DRV_WriteReg(RESZ_VLBSIZE, v);\
}
#define RESZ_NO_OWNER LAST_MOD_ID + 0x11
#define RESZ_BLK_EN 0x7
#if (defined(MT6219))
#define RESZ_PXL_EN 0x60
#define RESZ_BLK_RST 0x70000
#define RESZ_PXL_RST 0x600000
#elif (defined(MT6226)||defined(MT6226M)||defined(MT6227))
#define RESZ_PXL_EN 0x6
#define RESZ_BLK_RST 0x70000
#define RESZ_PXL_RST 0x60000
#endif
#define RESZ_ALL_RST RESZ_BLK_RST|RESZ_PXL_RST
// error code
#define NO_ERROR 0
#define RESZ_ERR_INVALID_SIZE 1
// extern
extern kal_int32 API RESZ_Init(void);
extern kal_int32 API RESZ_Open(MMDI_SCENERIO_ID owner);
extern kal_int32 API RESZ_Close(MMDI_SCENERIO_ID owner);
extern kal_int32 API RESZ_Config(RESZ_CFG_STRUCT *cfg, void *s, MMDI_SCENERIO_ID owner);
extern kal_int32 API RESZ_SetSize(kal_uint32 src_w, kal_uint32 src_h, kal_uint32 tar_w, kal_uint32 tar_h, MMDI_SCENERIO_ID owner);
extern kal_int32 API RESZ_SetSize2(kal_uint32 src_w, kal_uint32 src_h, kal_uint32 tar_w, kal_uint32 tar_h, MMDI_SCENERIO_ID owner);
extern kal_int32 API RESZ_Start(MMDI_SCENERIO_ID owner);
extern kal_int32 API RESZ_Stop(MMDI_SCENERIO_ID owner);
extern kal_bool API RESZ_CheckBusy(void);
extern kal_int32 INTERN RESZ_SetWMSize(kal_uint16 size, kal_bool pixel);
#elif (defined(MT6228)||defined(MT6229)||defined(MT6230))
#define RESZ_H_RATIO_SHIFT_BITS 20
#define RESZ_V_RATIO_SHIFT_BITS 20
/* DRZ definition */
#define PRZ_CONFIG_REG (PRZ_base + 0x00)
#define PRZ_CTRL_REG (PRZ_base + 0x04)
#define PRZ_STATUS_REG (PRZ_base + 0x08)
#define PRZ_INT_STATUS_REG (PRZ_base + 0x0C)
#define PRZ_SOURCE_IMAGE_SIZE_REG (PRZ_base + 0x10)
#define PRZ_TARGET_IMAGE_SIZE_REG (PRZ_base + 0x14)
#define PRZ_H_RATIO_REG (PRZ_base + 0x18)
#define PRZ_V_RATIO_REG (PRZ_base + 0x1C)
#define PRZ_H_RESIDUAL_REG (PRZ_base + 0x20)
#define PRZ_V_RESIDUAL_REG (PRZ_base + 0x24)
#define PRZ_BLOCK_CS_CFG_REG (PRZ_base + 0x30)
#define PRZ_Y_LINE_BUFFER_ADDR_REG (PRZ_base + 0x34)
#define PRZ_U_LINE_BUFFER_ADDR_REG (PRZ_base + 0x38)
#define PRZ_V_LINE_BUFFER_ADDR_REG (PRZ_base + 0x3C)
#define PRZ_FINE_RESIZE_CFG_REG (PRZ_base + 0x40)
#define PRZ_LINE_BUFFER_SIZE_REG (PRZ_base + 0x50)
#define PRZ_WORK_MEM_ADDR_REG (PRZ_base + 0x5C)
#define REG_PRZ_CONFIG *((volatile unsigned int *) (PRZ_base + 0x00))
#define REG_PRZ_CTRL *((volatile unsigned int *) (PRZ_base + 0x04))
#define REG_PRZ_STATUS *((volatile unsigned int *) (PRZ_base + 0x08))
#define REG_PRZ_INT_STATUS *((volatile unsigned int *) (PRZ_base + 0x0C))
#define REG_PRZ_SOURCE_IMAGE_SIZE *((volatile unsigned int *) (PRZ_base + 0x10))
#define REG_PRZ_TARGET_IMAGE_SIZE *((volatile unsigned int *) (PRZ_base + 0x14))
#define REG_PRZ_H_RATIO *((volatile unsigned int *) (PRZ_base + 0x18))
#define REG_PRZ_V_RATIO *((volatile unsigned int *) (PRZ_base + 0x1C))
#define REG_PRZ_H_RESIDUAL *((volatile unsigned int *) (PRZ_base + 0x20))
#define REG_PRZ_V_RESIDUAL *((volatile unsigned int *) (PRZ_base + 0x24))
#define REG_PRZ_BLOCK_CS_CFG *((volatile unsigned int *) (PRZ_base + 0x30))
#define REG_PRZ_Y_LINE_BUFFER_ADDR *((volatile unsigned int *) (PRZ_base + 0x34))
#define REG_PRZ_U_LINE_BUFFER_ADDR *((volatile unsigned int *) (PRZ_base + 0x38))
#define REG_PRZ_V_LINE_BUFFER_ADDR *((volatile unsigned int *) (PRZ_base + 0x3C))
#define REG_PRZ_FINE_RESIZE_CFG *((volatile unsigned int *) (PRZ_base + 0x40))
#define REG_PRZ_LINE_BUFFER_SIZE *((volatile unsigned int *) (PRZ_base + 0x50))
#define REG_PRZ_WORK_MEM_ADDR *((volatile unsigned int *) (PRZ_base + 0x5C))
/* bit mapping of PRZ config register */
#define PRZ_CONFIG_LINE_BUF_SEL_BIT 0x00000080
#define PRZ_CONFIG_PIXEL_SRC_MASK 0x0000000F
#define PRZ_CONFIG_SRC_SEL_BIT 0x00000020
#define PRZ_CONFIG_CONT_RUN_BIT 0x00000010
#define PRZ_CONFIG_PIXEL_SRC_CAMERA_ISP 0
#define PRZ_CONFIG_PIXEL_SRC_MPEG4_ENCODE_DMA 1
#define PRZ_CONFIG_PIXEL_SRC_MPEG4_DECODE_DMA 2
#define PRZ_CONFIG_PIXEL_SRC_IBW4_DMA 3
#define PRZ_CONFIG_PIXEL_SRC_IPP 4
#define PRZ_CONFIG_PIXEL_SRC_JPEG_DECODER 5
/* bit mapping of PRZ control register */
#define PRZ_CTRL_RESET_MASK 0x00070000
#define PRZ_CTRL_ENABLE_MASK 0x00000007
#define PRZ_CTRL_BLOCK_CS_ENABLE_BIT 0x00000001
#define PRZ_CTRL_H_FINE_RESIZE_ENABLE_BIT 0x00000002
#define PRZ_CTRL_V_FINE_RESIZE_ENABLE_BIT 0x00000004
#define PRZ_CTRL_BLOCK_CS_RESET_BIT 0x00010000
#define PRZ_CTRL_H_FINE_RESIZE_RESET_BIT 0x00020000
#define PRZ_CTRL_V_FINE_RESIZE_RESET_BIT 0x00040000
/* bit mapping of PRZ status register */
#define PRZ_CTRL_BLOCK_CS_BUSY_BIT 0x00000001
#define PRZ_CTRL_H_FINE_RESIZE_BUSY_BIT 0x00000002
#define PRZ_CTRL_V_FINE_RESIZE_BUSY_BIT 0x00000004
/* bit mapping of PRZ interrupt status register */
#define PRZ_CTRL_BLOCK_CS_INT_BIT 0x00000001
#define PRZ_CTRL_H_FINE_RESIZE_INT_BIT 0x00000002
#define PRZ_CTRL_V_FINE_RESIZE_INT_BIT 0x00000004
/* bit mapping of PRZ source and target size register */
#define PRZ_IMAGE_SIZE_WIDTH_MASK 0x0000FFFF
#define PRZ_IMAGE_SIZE_HEIGHT_MASK 0xFFFF0000
/* bit mapping of PRZ block coarse shrink config register */
#define PRZ_BLOCK_CS_CFG_BLOCK_INT_ENABLE_BIT 0x00010000
#define PRZ_BLOCk_CS_CFG_V_V_SAMPLE_FACTOR_MASK 0x0000C000
#define PRZ_BLOCk_CS_CFG_V_H_SAMPLE_FACTOR_MASK 0x00003000
#define PRZ_BLOCk_CS_CFG_U_V_SAMPLE_FACTOR_MASK 0x00000C00
#define PRZ_BLOCk_CS_CFG_U_H_SAMPLE_FACTOR_MASK 0x00000300
#define PRZ_BLOCk_CS_CFG_Y_V_SAMPLE_FACTOR_MASK 0x000000C0
#define PRZ_BLOCk_CS_CFG_Y_H_SAMPLE_FACTOR_MASK 0x00000030
#define PRZ_BLOCk_CS_CFG_CS_FACTOR_MASK 0x00000003
/* definition of resizer block CS register */
#define BLOCK_CS_1_1 0x00000000
#define BLOCK_CS_1_4 0x00000001
#define BLOCK_CS_1_16 0x00000002
#define BLOCK_CS_1_64 0x00000003
#define BLOCK_Y_H_FACTOR_1 0x00000000
#define BLOCK_Y_H_FACTOR_2 0x00000010
#define BLOCK_Y_H_FACTOR_4 0x00000020
#define BLOCK_NO_Y_H_COMP 0x00000030
#define BLOCK_Y_V_FACTOR_1 0x00000000
#define BLOCK_Y_V_FACTOR_2 0x00000040
#define BLOCK_Y_V_FACTOR_4 0x00000080
#define BLOCK_NO_Y_V_COMP 0x000000C0
#define BLOCK_U_H_FACTOR_1 0x00000000
#define BLOCK_U_H_FACTOR_2 0x00000100
#define BLOCK_U_H_FACTOR_4 0x00000200
#define BLOCK_NO_U_H_COMP 0x00000300
#define BLOCK_U_V_FACTOR_1 0x00000000
#define BLOCK_U_V_FACTOR_2 0x00000400
#define BLOCK_U_V_FACTOR_4 0x00000800
#define BLOCK_NO_U_V_COMP 0x00000CC0
#define BLOCK_V_H_FACTOR_1 0x00000000
#define BLOCK_V_H_FACTOR_2 0x00001000
#define BLOCK_V_H_FACTOR_4 0x00002000
#define BLOCK_NO_V_H_COMP 0x00003000
#define BLOCK_V_V_FACTOR_1 0x00000000
#define BLOCK_V_V_FACTOR_2 0x00004000
#define BLOCK_V_V_FACTOR_4 0x00008000
#define BLOCK_NO_V_V_COMP 0x0000C000
/* bit mapping of PRZ fine resize config register */
#define PRZ_FINE_RESIZE_WORK_MEM_SIZE_MASK 0xFFFF0000
#define PRZ_FINE_RESIZE_OUTPUT_SEL_BIT 0x00008000
#define PRZ_FINE_RESIZE_CS_MASK 0x00000300
#define PRZ_H_FINE_RESIZE_INT 0x00000010
#define PRZ_V_FINE_RESIZE_INT 0x00000020
/* bit mapping of PRZ line buffer size register */
#define PRZ_LINE_BUFF_SIZE_MASK 0x0000FFFF
/* Macros of PRZ control register */
#define SET_PRZ_SRC(src) REG_PRZ_CONFIG &= ~PRZ_CONFIG_PIXEL_SRC_MASK;\
REG_PRZ_CONFIG |= src;
#define SET_PRZ_PIXEL_MODE REG_PRZ_CONFIG |= PRZ_CONFIG_SRC_SEL_BIT;
#define SET_PRZ_BLOCK_MODE REG_PRZ_CONFIG &= ~PRZ_CONFIG_SRC_SEL_BIT;
#define SET_PRZ_CONT_MODE REG_PRZ_CONFIG |= PRZ_CONFIG_CONT_RUN_BIT;
#define SET_PRZ_SINGLE_MODE REG_PRZ_CONFIG &= ~PRZ_CONFIG_CONT_RUN_BIT;
#define SET_PRZ_SHARED_MEMORY REG_PRZ_CONFIG &= ~PRZ_CONFIG_LINE_BUF_SEL_BIT;
#define SET_PRZ_DEDICATED_MEMORY REG_PRZ_CONFIG |= PRZ_CONFIG_LINE_BUF_SEL_BIT;
/* Macros of PRZ control register */
#define RESET_PRZ REG_PRZ_CTRL=PRZ_CTRL_RESET_MASK;\
REG_PRZ_CTRL=0;
#define SET_BLOCK_CS_RESET REG_PRZ_CTRL |= PRZ_CTRL_BLOCK_CS_RESET_BIT;
#define CLEAR_BLOCK_CS_RESET REG_PRZ_CTRL &= ~PRZ_CTRL_BLOCK_CS_RESET_BIT;
#define SET_PRZ_H_FINE_RESIZE_RESET REG_PRZ_CTRL |= PRZ_CTRL_H_FINE_RESIZE_RESET_BIT;
#define CLEAR_PRZ_H_FINE_RESIZE_RESET REG_PRZ_CTRL &= ~PRZ_CTRL_H_FINE_RESIZE_RESET_BIT;
#define SET_PRZ_V_FINE_RESIZE_RESET REG_PRZ_CTRL |= PRZ_CTRL_V_FINE_RESIZE_RESET_BIT;
#define CLEAR_PRZ_V_FINE_RESIZE_RESET REG_PRZ_CTRL &= ~PRZ_CTRL_V_FINE_RESIZE_RESET_BIT;
#define ENABLE_BLOCK_CS_BLOCK REG_PRZ_CTRL |= PRZ_CTRL_BLOCK_CS_ENABLE_BIT;
#define DISABLE_BLOCK_CS_BLOCK REG_PRZ_CTRL &= ~PRZ_CTRL_BLOCK_CS_ENABLE_BIT;
#define ENABLE_PRZ_H_LINE REG_PRZ_CTRL |= PRZ_CTRL_H_FINE_RESIZE_ENABLE_BIT;
#define DISABLE_PRZ_H_LINE REG_PRZ_CTRL &= ~PRZ_CTRL_H_FINE_RESIZE_ENABLE_BIT;
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