📄 imgdma.h
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/* register definition of Video decode image dma */
#define IMGDMA_VIDEO_DECODE_START_REG (IMGDMA_base + 0x0280)
#define IMGDMA_VIDEO_DECODE_CTRL_REG (IMGDMA_base + 0x0284)
#define IMGDMA_VIDEO_DECODE_Y_BASE_ADDR1_REG (IMGDMA_base + 0x0290)
#define IMGDMA_VIDEO_DECODE_U_BASE_ADDR1_REG (IMGDMA_base + 0x0294)
#define IMGDMA_VIDEO_DECODE_V_BASE_ADDR1_REG (IMGDMA_base + 0x0298)
#define IMGDMA_VIDEO_DECODE_Y_BASE_ADDR2_REG (IMGDMA_base + 0x02A0)
#define IMGDMA_VIDEO_DECODE_U_BASE_ADDR2_REG (IMGDMA_base + 0x02A4)
#define IMGDMA_VIDEO_DECODE_V_BASE_ADDR2_REG (IMGDMA_base + 0x02A8)
#define IMGDMA_VIDEO_DECODE_WIDTH_REG (IMGDMA_base + 0x02B0)
#define IMGDMA_VIDEO_DECODE_HEIGHT_REG (IMGDMA_base + 0x02B4)
#define REG_IMGDMA_VIDEO_DECODE_START *((volatile unsigned int *)(IMGDMA_base + 0x0280))
#define REG_IMGDMA_VIDEO_DECODE_CTRL *((volatile unsigned int *)(IMGDMA_base + 0x0284))
#define REG_IMGDMA_VIDEO_DECODE_Y_BASE_ADDR1 *((volatile unsigned int *)(IMGDMA_base + 0x0290))
#define REG_IMGDMA_VIDEO_DECODE_U_BASE_ADDR1 *((volatile unsigned int *)(IMGDMA_base + 0x0294))
#define REG_IMGDMA_VIDEO_DECODE_V_BASE_ADDR1 *((volatile unsigned int *)(IMGDMA_base + 0x0298))
#define REG_IMGDMA_VIDEO_DECODE_Y_BASE_ADDR2 *((volatile unsigned int *)(IMGDMA_base + 0x02A0))
#define REG_IMGDMA_VIDEO_DECODE_U_BASE_ADDR2 *((volatile unsigned int *)(IMGDMA_base + 0x02A4))
#define REG_IMGDMA_VIDEO_DECODE_V_BASE_ADDR2 *((volatile unsigned int *)(IMGDMA_base + 0x02A8))
#define REG_IMGDMA_VIDEO_DECODE_WIDTH *((volatile unsigned int *)(IMGDMA_base + 0x02B0))
#define REG_IMGDMA_VIDEO_DECODE_HEIGHT *((volatile unsigned int *)(IMGDMA_base + 0x02B4))
/* bit mapping of video decode image dma control register */
#define IMGDMA_VIDEO_DECODE_INT_BIT 0x00000001
/* macros of Video decode image DMA start register */
#define START_IMGDMA_VIDEO_DECODE REG_IMGDMA_VIDEO_DECODE_START=1;
#define STOP_IMGDMA_VIDEO_DECODE REG_IMGDMA_VIDEO_DECODE_START=0;
/* macros of video decode image dma control register */
#define ENABLE_VIDEO_DECODE_INT REG_IMGDMA_VIDEO_DECODE_CTRL |= IMGDMA_VIDEO_DECODE_INT_BIT;
#define DISABLE_VIDEO_DECODE_INT REG_IMGDMA_VIDEO_DECODE_CTRL &= ~IMGDMA_VIDEO_DECODE_INT_BIT;
/* register definition of IBW1 image dma */
#define IMGDMA_IBW1_START_REG (IMGDMA_base + 0x0300)
#define IMGDMA_IBW1_CTRL_REG (IMGDMA_base + 0x0304)
#define IMGDMA_IBW1_BASE_ADDR1_REG (IMGDMA_base + 0x0308)
#define IMGDMA_IBW1_BASE_ADDR2_REG (IMGDMA_base + 0x030C)
#define IMGDMA_IBW1_WIDTH_REG (IMGDMA_base + 0x0310)
#define IMGDMA_IBW1_HEIGHT_REG (IMGDMA_base + 0x0314)
#define IMGDMA_IBW1_CLIP_LEFT_RIGHT_REG (IMGDMA_base + 0x0318)
#define IMGDMA_IBW1_CLIP_TOP_BUTTOM_REG (IMGDMA_base + 0x031C)
#define IMGDMA_IBW1_DEST_PITCH1_REG (IMGDMA_base + 0x0320)
#define IMGDMA_IBW1_DEST_PITCH2_REG (IMGDMA_base + 0x0324)
#define REG_IMGDMA_IBW1_START *((volatile unsigned int *)(IMGDMA_base + 0x0300))
#define REG_IMGDMA_IBW1_CTRL *((volatile unsigned int *)(IMGDMA_base + 0x0304))
#define REG_IMGDMA_IBW1_BASE_ADDR1 *((volatile unsigned int *)(IMGDMA_base + 0x0308))
#define REG_IMGDMA_IBW1_BASE_ADDR2 *((volatile unsigned int *)(IMGDMA_base + 0x030C))
#define REG_IMGDMA_IBW1_WIDTH *((volatile unsigned int *)(IMGDMA_base + 0x0310))
#define REG_IMGDMA_IBW1_HEIGHT *((volatile unsigned int *)(IMGDMA_base + 0x0314))
#define REG_IMGDMA_IBW1_CLIP_LEFT_RIGHT *((volatile unsigned int *)(IMGDMA_base + 0x0318))
#define REG_IMGDMA_IBW1_CLIP_TOP_BUTTOM *((volatile unsigned int *)(IMGDMA_base + 0x031C))
#define REG_IMGDMA_IBW1_DEST_PITCH1 *((volatile unsigned int *)(IMGDMA_base + 0x0320))
#define REG_IMGDMA_IBW1_DEST_PITCH2 *((volatile unsigned int *)(IMGDMA_base + 0x0324))
#define IMGDMA_IBW2_START_REG (IMGDMA_base + 0x0400)
#define IMGDMA_IBW2_CTRL_REG (IMGDMA_base + 0x0404)
#define IMGDMA_IBW2_BASE_ADDR1_REG (IMGDMA_base + 0x0408)
#define IMGDMA_IBW2_BASE_ADDR2_REG (IMGDMA_base + 0x040C)
#define IMGDMA_IBW2_WIDTH_REG (IMGDMA_base + 0x0410)
#define IMGDMA_IBW2_HEIGHT_REG (IMGDMA_base + 0x0414)
#define IMGDMA_IBW2_CLIP_LEFT_RIGHT_REG (IMGDMA_base + 0x0418)
#define IMGDMA_IBW2_CLIP_TOP_BUTTOM_REG (IMGDMA_base + 0x041C)
#define IMGDMA_IBW2_DEST_PITCH1_REG (IMGDMA_base + 0x0420)
#define IMGDMA_IBW2_DEST_PITCH2_REG (IMGDMA_base + 0x0424)
#define IMGDMA_IBW_PIXEL_COUNT_REG (IMGDMA_base + 0x0428)
#define IMGDMA_IBW_LINE_COUNT_REG (IMGDMA_base + 0x042C)
#define REG_IMGDMA_IBW2_START *((volatile unsigned int *)(IMGDMA_base + 0x0400))
#define REG_IMGDMA_IBW2_CTRL *((volatile unsigned int *)(IMGDMA_base + 0x0404))
#define REG_IMGDMA_IBW2_BASE_ADDR1 *((volatile unsigned int *)(IMGDMA_base + 0x0408))
#define REG_IMGDMA_IBW2_BASE_ADDR2 *((volatile unsigned int *)(IMGDMA_base + 0x040C))
#define REG_IMGDMA_IBW2_WIDTH *((volatile unsigned int *)(IMGDMA_base + 0x0410))
#define REG_IMGDMA_IBW2_HEIGHT *((volatile unsigned int *)(IMGDMA_base + 0x0414))
#define REG_IMGDMA_IBW2_CLIP_LEFT_RIGHT *((volatile unsigned int *)(IMGDMA_base + 0x0418))
#define REG_IMGDMA_IBW2_CLIP_TOP_BUTTOM *((volatile unsigned int *)(IMGDMA_base + 0x041C))
#define REG_IMGDMA_IBW2_DEST_PITCH1 *((volatile unsigned int *)(IMGDMA_base + 0x0420))
#define REG_IMGDMA_IBW2_DEST_PITCH2 *((volatile unsigned int *)(IMGDMA_base + 0x0424))
#define REG_IMGDMA_IBW2_PIXEL_COUNT *((volatile unsigned int *)(IMGDMA_base + 0x0428))
#define REG_IMGDMA_IBW2_LINE_COUNT *((volatile unsigned int *)(IMGDMA_base + 0x042C))
/* bit mapping of IBW1 and IBW2 control register */
#define IMGDMA_IBW_PIXEL_SRC_MASK 0x00000180
#define IMGDMA_IBW_OUTPUT_FORMAT_BIT 0x00000040
#define IMGDMA_IBW_PAN_ENABLE_BIT 0x00000020
#define IMGDMA_IBW_DC_ENABLE_BIT 0x00000010
#define IMGDMA_IBW_AUTO_RESTART_BIT 0x00000008
#define IMGDMA_IBW_TRIGGER_LCD_BIT 0x00000004
#define IMGDMA_IBW_DEST_PITCH_BIT 0x00000002
#define IMGDMA_IBW_INT_BIT 0x00000001
#define IMGDMA_IBW_PIXEL_SRC_IPP1 0x00000000
#define IMGDMA_IBW_PIXEL_SRC_IPP2 0x00000080
#define IMGDMA_IBW_PIXEL_SRC_CRZ 0x00000100
#define IMGDMA_IBW_PIXEL_SRC_PRZ 0x00000180
#define IMGDMA_IBW_OUTPUT_RGB565 0x00000000
#define IMGDMA_IBW_OUTPUT_RGB888 0x00000040
/* macros of IBW1,IBW2 start register */
#define START_IBW1 REG_IMGDMA_IBW1_START=1;
#define STOP_IBW1 REG_IMGDMA_IBW1_START=0;
#define START_IBW2 REG_IMGDMA_IBW2_START=1;
#define STOP_IBW2 REG_IMGDMA_IBW2_START=0;
/* macros of IBW1 and IBW2 control register */
#define SET_IBW1_PIXEL_SRC_IPP1 REG_IMGDMA_IBW1_CTRL &= ~IMGDMA_IBW_PIXEL_SRC_MASK;
#define SET_IBW1_PIXEL_SRC_IPP2 REG_IMGDMA_IBW1_CTRL &= ~IMGDMA_IBW_PIXEL_SRC_MASK;\
REG_IMGDMA_IBW1_CTRL |= IMGDMA_IBW_PIXEL_SRC_IPP2;
#define SET_IBW1_PIXEL_SRC_CRZ REG_IMGDMA_IBW1_CTRL &= ~IMGDMA_IBW_PIXEL_SRC_MASK;\
REG_IMGDMA_IBW1_CTRL |= IMGDMA_IBW_PIXEL_SRC_CRZ;
#define SET_IBW1_PIXEL_SRC_PRZ REG_IMGDMA_IBW1_CTRL &= ~IMGDMA_IBW_PIXEL_SRC_MASK;\
REG_IMGDMA_IBW1_CTRL |= IMGDMA_IBW_PIXEL_SRC_PRZ;
#define SET_IBW1_PIXEL_SRC(pixel_src) REG_IMGDMA_IBW1_CTRL &= ~IMGDMA_IBW_PIXEL_SRC_MASK;\
REG_IMGDMA_IBW1_CTRL |= pixel_src;
#define SET_IBW1_OUTPUT_RGB565 REG_IMGDMA_IBW1_CTRL &= ~IMGDMA_IBW_OUTPUT_FORMAT_BIT;
#define SET_IBW1_OUTPUT_RGB888 REG_IMGDMA_IBW1_CTRL |= IMGDMA_IBW_OUTPUT_FORMAT_BIT;
#define SET_IBW1_OUTPUT_FORMAT(format) REG_IMGDMA_IBW1_CTRL &= ~IMGDMA_IBW_OUTPUT_FORMAT_BIT;\
REG_IMGDMA_IBW1_CTRL |= format;
#define ENABLE_IBW1_PAN REG_IMGDMA_IBW1_CTRL |= IMGDMA_IBW_PAN_ENABLE_BIT;
#define DISABLE_IBW1_PAN REG_IMGDMA_IBW1_CTRL &= ~IMGDMA_IBW_PAN_ENABLE_BIT;
#define ENABLE_IBW1_DC REG_IMGDMA_IBW1_CTRL |= IMGDMA_IBW_DC_ENABLE_BIT;
#define DISABLE_IBW1_DC REG_IMGDMA_IBW1_CTRL &= ~IMGDMA_IBW_DC_ENABLE_BIT;
#define ENABLE_IBW1_AUTO_RESTART REG_IMGDMA_IBW1_CTRL |= IMGDMA_IBW_AUTO_RESTART_BIT;
#define DISABLE_IBW1_AUTO_RESTART REG_IMGDMA_IBW1_CTRL &= ~IMGDMA_IBW_AUTO_RESTART_BIT;
#define ENABLE_IBW1_TRIGGER_LCD REG_IMGDMA_IBW1_CTRL |= IMGDMA_IBW_TRIGGER_LCD_BIT;
#define DISABLE_IBW1_TRIGGER_LCD REG_IMGDMA_IBW1_CTRL &= ~IMGDMA_IBW_TRIGGER_LCD_BIT;
#define ENABLE_IBW1_DEST_PITCH REG_IMGDMA_IBW1_CTRL |= IMGDMA_IBW_DEST_PITCH_BIT;
#define DISABLE_IBW1_DEST_PITCH REG_IMGDMA_IBW1_CTRL &= ~IMGDMA_IBW_DEST_PITCH_BIT;
#define ENABLE_IBW1_INT REG_IMGDMA_IBW1_CTRL |= IMGDMA_IBW_INT_BIT;
#define DISABLE_IBW1_INT REG_IMGDMA_IBW1_CTRL &= ~IMGDMA_IBW_INT_BIT;
#define SET_IBW2_PIXEL_SRC_IPP1 REG_IMGDMA_IBW2_CTRL &= ~IMGDMA_IBW_PIXEL_SRC_MASK;
#define SET_IBW2_PIXEL_SRC_IPP2 REG_IMGDMA_IBW2_CTRL &= ~IMGDMA_IBW_PIXEL_SRC_MASK;\
REG_IMGDMA_IBW2_CTRL |= IMGDMA_IBW_PIXEL_SRC_IPP2;
#define SET_IBW2_PIXEL_SRC_CRZ REG_IMGDMA_IBW2_CTRL &= ~IMGDMA_IBW_PIXEL_SRC_MASK;\
REG_IMGDMA_IBW2_CTRL |= IMGDMA_IBW_PIXEL_SRC_CRZ;
#define SET_IBW2_PIXEL_SRC_PRZ REG_IMGDMA_IBW2_CTRL &= ~IMGDMA_IBW_PIXEL_SRC_MASK;\
REG_IMGDMA_IBW2_CTRL |= IMGDMA_IBW_PIXEL_SRC_PRZ;
#define SET_IBW2_PIXEL_SRC(pixel_src) REG_IMGDMA_IBW2_CTRL &= ~IMGDMA_IBW_PIXEL_SRC_MASK;\
REG_IMGDMA_IBW2_CTRL |= pixel_src;
#define SET_IBW2_OUTPUT_RGB565 REG_IMGDMA_IBW2_CTRL &= ~IMGDMA_IBW_OUTPUT_FORMAT_BIT;
#define SET_IBW2_OUTPUT_RGB888 REG_IMGDMA_IBW2_CTRL |= IMGDMA_IBW_OUTPUT_FORMAT_BIT;
#define SET_IBW2_OUTPUT_FORMAT(format) REG_IMGDMA_IBW2_CTRL &= ~IMGDMA_IBW_OUTPUT_FORMAT_BIT;\
REG_IMGDMA_IBW2_CTRL |= format;
#define ENABLE_IBW2_PAN REG_IMGDMA_IBW2_CTRL |= IMGDMA_IBW_PAN_ENABLE_BIT;
#define DISABLE_IBW2_PAN REG_IMGDMA_IBW2_CTRL &= ~IMGDMA_IBW_PAN_ENABLE_BIT;
#define ENABLE_IBW2_DC REG_IMGDMA_IBW2_CTRL |= IMGDMA_IBW_DC_ENABLE_BIT;
#define DISABLE_IBW2_DC REG_IMGDMA_IBW2_CTRL &= ~IMGDMA_IBW_DC_ENABLE_BIT;
#define ENABLE_IBW2_AUTO_RESTART REG_IMGDMA_IBW2_CTRL |= IMGDMA_IBW_AUTO_RESTART_BIT;
#define DISABLE_IBW2_AUTO_RESTART REG_IMGDMA_IBW2_CTRL &= ~IMGDMA_IBW_AUTO_RESTART_BIT;
#define ENABLE_IBW2_TRIGGER_LCD REG_IMGDMA_IBW2_CTRL |= IMGDMA_IBW_TRIGGER_LCD_BIT;
#define DISABLE_IBW2_TRIGGER_LCD REG_IMGDMA_IBW2_CTRL &= ~IMGDMA_IBW_TRIGGER_LCD_BIT;
#define ENABLE_IBW2_DEST_PITCH REG_IMGDMA_IBW2_CTRL |= IMGDMA_IBW_DEST_PITCH_BIT;
#define DISABLE_IBW2_DEST_PITCH REG_IMGDMA_IBW2_CTRL &= ~IMGDMA_IBW_DEST_PITCH_BIT;
#define ENABLE_IBW2_INT REG_IMGDMA_IBW2_CTRL |= IMGDMA_IBW_INT_BIT;
#define DISABLE_IBW2_INT REG_IMGDMA_IBW2_CTRL &= ~IMGDMA_IBW_INT_BIT;
/* register definition of IBW3 */
#define IMGDMA_IBW3_START_REG (IMGDMA_base + 0x0500)
#define IMGDMA_IBW3_CTRL_REG (IMGDMA_base + 0x0504)
#define IMGDMA_IBW3_WIDTH_REG (IMGDMA_base + 0x0510)
#define IMGDMA_IBW3_HEIGHT_REG (IMGDMA_base + 0x0514)
#define REG_IMGDMA_IBW3_START *((volatile unsigned int *)(IMGDMA_base + 0x0500))
#define REG_IMGDMA_IBW3_CTRL *((volatile unsigned int *)(IMGDMA_base + 0x0504))
#define REG_IMGDMA_IBW3_WIDTH *((volatile unsigned int *)(IMGDMA_base + 0x0510))
#define REG_IMGDMA_IBW3_HEIGHT *((volatile unsigned int *)(IMGDMA_base + 0x0514))
/* macros of IBW3,IBW4 start register */
#define START_IBW3 REG_IMGDMA_IBW3_START=1;
#define STOP_IBW3 REG_IMGDMA_IBW3_START=0;
#define START_IBW4 REG_IMGDMA_IBW4_START=1;
#define STOP_IBW4 REG_IMGDMA_IBW4_START=0;
/* macros of IBW3 control register */
#define SET_IBW3_PIXEL_SRC_IPP1 REG_IMGDMA_IBW3_CTRL &= ~IMGDMA_IBW_PIXEL_SRC_MASK;
#define SET_IBW3_PIXEL_SRC_IPP2 REG_IMGDMA_IBW3_CTRL &= ~IMGDMA_IBW_PIXEL_SRC_MASK;\
REG_IMGDMA_IBW3_CTRL |= IMGDMA_IBW_PIXEL_SRC_IPP2;
#define SET_IBW3_PIXEL_SRC_CRZ REG_IMGDMA_IBW3_CTRL &= ~IMGDMA_IBW_PIXEL_SRC_MASK;\
REG_IMGDMA_IBW3_CTRL |= IMGDMA_IBW_PIXEL_SRC_CRZ;
#define SET_IBW3_PIXEL_SRC_PRZ REG_IMGDMA_IBW3_CTRL &= ~IMGDMA_IBW_PIXEL_SRC_MASK;\
REG_IMGDMA_IBW3_CTRL |= IMGDMA_IBW_PIXEL_SRC_PRZ;
#define SET_IBW3_PIXEL_SRC(pixel_src) REG_IMGDMA_IBW3_CTRL &= ~IMGDMA_IBW_PIXEL_SRC_MASK;\
REG_IMGDMA_IBW3_CTRL |= pixel_src;
#define ENABLE_IBW3_AUTO_RESTART REG_IMGDMA_IBW3_CTRL |= IMGDMA_IBW_AUTO_RESTART_BIT;
#define DISABLE_IBW3_AUTO_RESTART REG_IMGDMA_IBW3_CTRL &= ~IMGDMA_IBW_AUTO_RESTART_BIT;
#define ENABLE_IBW3_INT REG_IMGDMA_IBW3_CTRL |= IMGDMA_IBW_INT_BIT;
#define DISABLE_IBW3_INT REG_IMGDMA_IBW3_CTRL &= ~IMGDMA_IBW_INT_BIT;
/* register definition of IBW4 */
#define IMGDMA_IBW4_START_REG (IMGDMA_base + 0x0580)
#define IMGDMA_IBW4_CTRL_REG (IMGDMA_base + 0x0584)
#define IMGDMA_IBW4_WIDTH_REG (IMGDMA_base + 0x0590)
#define IMGDMA_IBW4_HEIGHT_REG (IMGDMA_base + 0x0594)
#define REG_IMGDMA_IBW4_START *((volatile unsigned int *)(IMGDMA_base + 0x0580))
#define REG_IMGDMA_IBW4_CTRL *((volatile unsigned int *)(IMGDMA_base + 0x0584))
#define REG_IMGDMA_IBW4_WIDTH *((volatile unsigned int *)(IMGDMA_base + 0x0590))
#define REG_IMGDMA_IBW4_HEIGHT *((volatile unsigned int *)(IMGDMA_base + 0x0594))
/* macros of IBW4 control register */
#define SET_IBW4_PIXEL_SRC_IPP1 REG_IMGDMA_IBW4_CTRL &= ~IMGDMA_IBW_PIXEL_SRC_MASK;
#define SET_IBW4_PIXEL_SRC_IPP2 REG_IMGDMA_IBW4_CTRL &= ~IMGDMA_IBW_PIXEL_SRC_MASK;\
REG_IMGDMA_IBW4_CTRL |= IMGDMA_IBW_PIXEL_SRC_IPP2;
#define SET_IBW4_PIXEL_SRC_CRZ REG_IMGDMA_IBW4_CTRL &= ~IMGDMA_IBW_PIXEL_SRC_MASK;\
REG_IMGDMA_IBW4_CTRL |= IMGDMA_IBW_PIXEL_SRC_CRZ;
#define SET_IBW4_PIXEL_SRC_PRZ REG_IMGDMA_IBW4_CTRL &= ~IMGDMA_IBW_PIXEL_SRC_MASK;\
REG_IMGDMA_IBW4_CTRL |= IMGDMA_IBW_PIXEL_SRC_PRZ;
#define SET_IBW4_PIXEL_SRC(pixel_src) REG_IMGDMA_IBW4_CTRL &= ~IMGDMA_IBW_PIXEL_SRC_MASK;\
REG_IMGDMA_IBW4_CTRL |= pixel_src;
#define ENABLE_IBW4_AUTO_RESTART REG_IMGDMA_IBW4_CTRL |= IMGDMA_IBW_AUTO_RESTART_BIT;
#define DISABLE_IBW4_AUTO_RESTART REG_IMGDMA_IBW4_CTRL &= ~IMGDMA_IBW_AUTO_RESTART_BIT;
#define ENABLE_IBW4_INT REG_IMGDMA_IBW4_CTRL |= IMGDMA_IBW_INT_BIT;
#define DISABLE_IBW4_INT REG_IMGDMA_IBW4_CTRL &= ~IMGDMA_IBW_INT_BIT;
/* register definition of IBR1 */
#define IMGDMA_IBR1_START_REG (IMGDMA_base + 0x0600)
#define IMGDMA_IBR1_CTRL_REG (IMGDMA_base + 0x0604)
#define IMGDMA_IBR1_BASE_ADDR_REG (IMGDMA_base + 0x0608)
#define IMGDMA_IBR1_PIXEL_NUMBER_REG (IMGDMA_base + 0x060C)
#define REG_IMGDMA_IBR1_START *((volatile unsigned int *)(IMGDMA_base + 0x0600))
#define REG_IMGDMA_IBR1_CTRL *((volatile unsigned int *)(IMGDMA_base + 0x0604))
#define REG_IMGDMA_IBR1_BASE_ADDR *((volatile unsigned int *)(IMGDMA_base + 0x0608))
#define REG_IMGDMA_IBR1_PIXEL_NUMBER *((volatile unsigned int *)(IMGDMA_base + 0x060C))
/* bit mapping of IBR1 control register*/
#define IMGDMA_IBR1_DATA_ORDER_BIT 0x00000004
#define IMGDMA_IBR1_DATA_FORMAT_BIT 0x00000002
#define IMGDMA_IBR1_INT_BIT 0x00000001
#define IMGDMA_IBR1_INTPUT_RGB565 0x00000000
#define IMGDMA_IBR1_INTPUT_RGB888 0x00000002
/* macros of IBR1 start register */
#define START_IBR1 REG_IMGDMA_IBR1_START=1;
#define STOP_IBR1 REG_IMGDMA_IBR1_START=0;
/* macros of IBR1 control register */
#define SET_IMGDMA_IBR1_DATA_ORDER_RGB888 REG_IMGDMA_IBR1_CTRL &= ~IMGDMA_IBR1_DATA_ORDER_BIT;
#define SET_IMGDMA_IBR1_DATA_ORDER_BGR888 REG_IMGDMA_IBR1_CTRL |= IMGDMA_IBR1_DATA_ORDER_BIT;
#define SET_IMGDMA_IBR1_DATA_RGB565 REG_IMGDMA_IBR1_CTRL &= ~IMGDMA_IBR1_DATA_FORMAT_BIT;
#define SET_IMGDMA_IBR1_DATA_RGB888 REG_IMGDMA_IBR1_CTRL |= IMGDMA_IBR1_DATA_FORMAT_BIT;
#define ENABLE_IMGDMA_IBR1_INT REG_IMGDMA_IBR1_CTRL |= IMGDMA_IBR1_INT_BIT;
#define DISABLE_IMGDMA_IBR1_INT REG_IMGDMA_IBR1_CTRL &= ~IMGDMA_IBR1_INT_BIT;
/* register definition of IBW2 */
#define IMGDMA_IBR2_START_REG (IMGDMA_base + 0x0700)
#define IMGDMA_IBR2_CTRL_REG (IMGDMA_base + 0x0704)
#define IMGDMA_IBR2_BASE_ADDR_REG (IMGDMA_base + 0x0708)
#define IMGDMA_IBR2_CONFIG_REG (IMGDMA_base + 0x070C)
#define IMGDMA_IBR2_WIDTH_REG (IMGDMA_base + 0x0710)
#define IMGDMA_IBR2_HEIGHT_REG (IMGDMA_base + 0x0714)
#define IMGDMA_IBR2_COLOR_PALETTE_BASE (IMGDMA_base + 0x0800)
#define REG_IMGDMA_IBR2_START *((volatile unsigned int *)(IMGDMA_base + 0x0700))
#define REG_IMGDMA_IBR2_CTRL *((volatile unsigned int *)(IMGDMA_base + 0x0704))
#define REG_IMGDMA_IBR2_BASE_ADDR *((volatile unsigned int *)(IMGDMA_base + 0x0708))
#define REG_IMGDMA_IBR2_CONFIG *((volatile unsigned int *)(IMGDMA_base + 0x070C))
#define REG_IMGDMA_IBR2_WIDTH *((volatile unsigned int *)(IMGDMA_base + 0x0710))
#define REG_IMGDMA_IBR2_HEIGHT *((volatile unsigned int *)(IMGDMA_base + 0x0714))
/* bit mapping of IBR2 control register */
#define IMGDMA_IBR2_PIXEL_SEL_BIT 0x00000080
#define IMGDMA_IBR2_PALETTE_ENABLE_BIT 0x00000010
#define IMGDMA_IBR2_AUTO_RESTART_BIT 0x00000008
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