imgdma.h

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}IMGDMA_DATA_ORDER_ENUM;

typedef enum{
	IMGDMA_INIT,
	IMGDMA_READY,
	IMGDMA_BUSY
}IMGDMA_STATE_ENUM;

typedef enum{
	IMGDMA_STOP_NOW,
	IMGDMA_STOP_CALLBACK,	// for channel without enable auto_restart
	IMGDMA_STOP_AT_FRAME_BOUNDARY, // for channel eanbled auto_restart
	IMGDMA_STOP_IDLE
}IMGDMA_STOP_ENUM;

typedef struct{
	kal_uint32 bs;	// line buffer base address
	kal_uint16 width;	// image width(minus 1 before writing to register)
	kal_uint16 height; // image height
	kal_uint16 fifo;	// fifo length
	kal_bool gray; // 1: for gray mode, 0: for color mode
	IDMA_Callback cb;	// interrupt callback function NULL: disable interrupt
}IMGDMA_JPEG_STRUCT;

typedef struct{
	IMGDMA_DIR_ENUM dir;	// 1: for MEPG4 encode, 0: for MPEG4 decode
	kal_bool	twice;	// 1: enable twice resizing 0: disable
	kal_bool restart; // 1: automatic reastart while current frame is finished
	kal_uint32 bs1;	// first base address
	kal_uint32 bs2;	// second base address
	kal_uint16 width;	// frame width (1 stands for 1)(max 255)
	kal_uint16 height;	// frame height
	void (*cb1)(kal_uint32 yuv_address);	// interrupt callback function NULL: disable interrupt(first run)
	IDMA_Callback cb2;	// interrupt callback function NULL: disable interrupt(second run)
}IMGDMA_VDO_STRUCT;

typedef struct{
	kal_uint32 bs;	// buffer base address
	kal_uint32 pxlnum; // number of pixels(minus 1 before writing to register)
	IDMA_Callback cb;	// interrupt callback function NULL: disable interrupt
}IMGDMA_IBW1_STRUCT;

typedef struct{
	kal_bool	twice; // 1: enable twice resizing 0: disable
	kal_bool restart; // 1: automatic reastart while current frame is finished
	kal_bool lcd_hk; // signaling LCD DMA while current frame is complete.
	kal_bool couple; // directly coupling to LCD DMA
	kal_bool pan; // picture panning
	kal_uint32 bs1; // first base address
	kal_uint32 bs2; // second base address
	kal_uint16 width;	// image width(minus 1 before writing to register)
	kal_uint16 height; // image height
	kal_uint16 hpitch1; // horizontal pitch 1
	kal_uint16 hpitch2; // horizontal pitch 2
	kal_uint16 vpitch1; // vertical pitch 1
	kal_uint16 vpitch2; // vertical pitch 2
	IDMA_Callback cb;	// interrupt callback function NULL: disable interrupt
}IMGDMA_IBW2_STRUCT;

typedef struct{
	IMGDMA_DATA_TYPE_ENUM	type; //RGB565 or RGB888
	IMGDMA_DATA_ORDER_ENUM	order; //BGR888 or RGB888
	kal_uint32 bs;	// base address
	kal_uint32 pxlnum; // number of pixels(minus 1 before writing to register)
	IDMA_Callback cb;	// interrupt callback function NULL: disable interrupt
}IMGDMA_IBR1_STRUCT;

typedef struct{
	kal_bool twice;
	kal_bool stop_cb[IMGDMA_ALL_CH];
	MMDI_SCENERIO_ID owner;
	IMGDMA_STATE_ENUM state[IMGDMA_ALL_CH];
	IDMA_Callback cb[IMGDMA_ALL_CH+1]; // one for first run of VDO
}IMGDMA_DCB_STRUCT;

// macros
#define IMGDMA_STR(ch)					(IMGDMA_BASE+0x100*(ch+1))
#define IMGDMA_CON(ch)					(IMGDMA_BASE+0x100*(ch+1)+4)
#define IMGDMA_START(ch)				{DRV_WriteReg32(IMGDMA_STR(ch), 0); \
                                    DRV_WriteReg32(IMGDMA_STR(ch), 1);}
#define IMGDMA_STOP(ch)					DRV_WriteReg32(IMGDMA_STR(ch), 0)
#define IMGDMA_ENABLE_INT(ch) 		DRV_Reg((0x100*(ch+1)+ 4))|= 1
#define IMGDMA_DISABLE_INT(ch) 		DRV_Reg((0x100*(ch+1)+ 4))&= ~1
#define IMGDMA_IS_BUSY(ch)				((DRV_Reg32(IMGDMA_STA)>>16) & (1<<ch))
#define IMGDMA_ACKI(n)					DRV_WriteReg32(IMGDMA_ACKINT,n) // n: IMGDMA_STA_JPEGIT, ...

// definitons
#define NO_ERROR 							0
#define IMGDMA_ACCESS_DENY				1

#define ENABLE_IBW2_INT			*((volatile unsigned int *)IMGDMA_IBW2_CON) |= IMGDMA_IBW2_CON_IT;
#define DISABLE_IBW2_INT		*((volatile unsigned int *)IMGDMA_IBW2_CON) &= ~IMGDMA_IBW2_CON_IT;

#define IMGDMA_IBW2_IS_BUSY		(*((volatile unsigned int *) IMGDMA_STA)&(1<<(IMGDMA_IBW2_CH+16)))

// extern functions
extern kal_int32 API IMGDMA_Init(void);
extern kal_int32 API IMGDMA_JpegConfig(IMGDMA_JPEG_STRUCT *s, kal_bool start, MMDI_SCENERIO_ID owner);
extern kal_int32 API IMGDMA_VdoConfig(IMGDMA_VDO_STRUCT *s, kal_bool start, MMDI_SCENERIO_ID owner);
extern kal_int32 API IMGDMA_IBW1Config(IMGDMA_IBW1_STRUCT *s, kal_bool start, MMDI_SCENERIO_ID owner);
extern kal_int32 API IMGDMA_IBW2Config(IMGDMA_IBW2_STRUCT *s, kal_bool start, MMDI_SCENERIO_ID owner);
extern kal_int32 API IMGDMA_IBR1Config(IMGDMA_IBR1_STRUCT *s, kal_bool start, MMDI_SCENERIO_ID owner);
extern kal_int32 API IMGDMA_Start(IMGDMA_CHANNEL_ENUM ch, MMDI_SCENERIO_ID owner);
extern kal_int32 API IMGDMA_Stop(IMGDMA_CHANNEL_ENUM ch, IMGDMA_STOP_ENUM stop, IDMA_Callback stop_cb, MMDI_SCENERIO_ID owner);
extern kal_int32 API IMGDMA_WaitComplete(IMGDMA_CHANNEL_ENUM ch, MMDI_SCENERIO_ID owner);
extern kal_int32 API IMGDMA_Open(MMDI_SCENERIO_ID owner);
extern kal_int32 API IMGDMA_Close(MMDI_SCENERIO_ID owner);
extern kal_bool API IMGDMA_CheckBusy(IMGDMA_CHANNEL_ENUM ch, MMDI_SCENERIO_ID owner);
#elif (defined(MT6228)||defined(MT6229)||defined(MT6230))
	/* register definition of Image DMA */
	#define IMGDMA_STATUS_REG							(IMGDMA_base + 0x0000)
	#define IMGDMA_INT_ACK_REG							(IMGDMA_base + 0x0004)

	#define REG_IMGDMA_STATUS							*((volatile unsigned int *)(IMGDMA_base + 0x0000))
	#define REG_IMGDMA_INT_ACK							*((volatile unsigned int *)(IMGDMA_base + 0x0004))

	/* bit mapping of image dma status register */
	#define IMGDMA_IBW4_BUSY_BIT						0x02000000
	#define IMGDMA_IBW3_BUSY_BIT						0x01000000
	#define IMGDMA_IBR2_BUSY_BIT						0x00800000
	#define IMGDMA_IBR1_BUSY_BIT						0x00400000
	#define IMGDMA_IBW2_BUSY_BIT						0x00200000
	#define IMGDMA_IBW1_BUSY_BIT						0x00100000
	#define IMGDMA_VIDEO_DECODE_BUSY_BIT			0x00080000
	#define IMGDMA_VIDEO_ENCODE_R_BUSY_BIT			0x00040000
	#define IMGDMA_VIDEO_ENCODE_W_BUSY_BIT			0x00020000
	#define IMGDMA_JPEG_BUSY_BIT						0x00010000

	#define IMGDMA_IBW4_INT_STATUS_BIT					0x00000200
	#define IMGDMA_IBW3_INT_STATUS_BIT					0x00000100
	#define IMGDMA_IBR2_INT_STATUS_BIT					0x00000080
	#define IMGDMA_IBR1_INT_STATUS_BIT					0x00000040
	#define IMGDMA_IBW2_INT_STATUS_BIT					0x00000020
	#define IMGDMA_IBW1_INT_STATUS_BIT					0x00000010
	#define IMGDMA_VIDEO_DECODE_INT_STATUS_BIT		0x00000008
	#define IMGDMA_VIDEO_ENCODE_R_INT_STATUS_BIT		0x00000004
	#define IMGDMA_VIDEO_ENCODE_W_INT_STATUS_BIT		0x00000002
	#define IMGDMA_JPEG_INT_STATUS_BIT					0x00000001

	/* bit mapping of image dma interrupt ACK register */
	#define IMGDMA_IBW4_INT_ACK_BIT					0x00000200
	#define IMGDMA_IBW3_INT_ACK_BIT					0x00000100
	#define IMGDMA_IBR2_INT_ACK_BIT					0x00000080
	#define IMGDMA_IBR1_INT_ACK_BIT					0x00000040
	#define IMGDMA_IBW2_INT_ACK_BIT					0x00000020
	#define IMGDMA_IBW1_INT_ACK_BIT					0x00000010
	#define IMGDMA_VIDEO_DECODE_INT_ACK_BIT		0x00000008
	#define IMGDMA_VIDEO_ENCODE_R_INT_ACK_BIT		0x00000004
	#define IMGDMA_VIDEO_ENCODE_W_INT_ACK_BIT		0x00000002
	#define IMGDMA_JPEG_INT_ACK_BIT					0x00000001

	/* macros of image dma status register */
	#define IMGDMA_IBW4_IS_BUSY						(REG_IMGDMA_STATUS & IMGDMA_IBW4_BUSY_BIT)
	#define IMGDMA_IBW3_IS_BUSY						(REG_IMGDMA_STATUS & IMGDMA_IBW3_BUSY_BIT)
	#define IMGDMA_IBR2_IS_BUSY						(REG_IMGDMA_STATUS & IMGDMA_IBR2_BUSY_BIT)
	#define IMGDMA_IBR1_IS_BUSY						(REG_IMGDMA_STATUS & IMGDMA_IBR1_BUSY_BIT)
	#define IMGDMA_IBW2_IS_BUSY						(REG_IMGDMA_STATUS & IMGDMA_IBW2_BUSY_BIT)
	#define IMGDMA_IBW1_IS_BUSY						(REG_IMGDMA_STATUS & IMGDMA_IBW1_BUSY_BIT)
	#define IMGDMA_VIDEO_DECODE_IS_BUSY				(REG_IMGDMA_STATUS & IMGDMA_VIDEO_DECODE_BUSY_BIT)
	#define IMGDMA_VIDEO_ENCODE_R_IS_BUSY			(REG_IMGDMA_STATUS & IMGDMA_VIDEO_ENCODE_R_BUSY_BIT)
	#define IMGDMA_VIDEO_ENCODE_W_IS_BUSY			(REG_IMGDMA_STATUS & IMGDMA_VIDEO_ENCODE_W_BUSY_BIT)
	#define IMGDMA_JPEG_IS_BUSY						(REG_IMGDMA_STATUS & IMGDMA_JPEG_BUSY_BIT)

	/* macros of image dma interrupt ACK register */
	#define ACK_IMGDMA_IBW4_INT						REG_IMGDMA_INT_ACK = IMGDMA_IBW4_INT_ACK_BIT;
	#define ACK_IMGDMA_IBW3_INT						REG_IMGDMA_INT_ACK = IMGDMA_IBW3_INT_ACK_BIT;
	#define ACK_IMGDMA_IBR2_INT						REG_IMGDMA_INT_ACK = IMGDMA_IBR2_INT_ACK_BIT;
	#define ACK_IMGDMA_IBR1_INT						REG_IMGDMA_INT_ACK = IMGDMA_IBR1_INT_ACK_BIT;
	#define ACK_IMGDMA_IBW2_INT						REG_IMGDMA_INT_ACK = IMGDMA_IBW2_INT_ACK_BIT;
	#define ACK_IMGDMA_IBW1_INT						REG_IMGDMA_INT_ACK = IMGDMA_IBW1_INT_ACK_BIT;
	#define ACK_IMGDMA_VIDEO_DECODE_INT				REG_IMGDMA_INT_ACK = IMGDMA_VIDEO_DECODE_INT_ACK_BIT;
	#define ACK_IMGDMA_VIDEO_ENCODE_R_INT			REG_IMGDMA_INT_ACK = IMGDMA_VIDEO_ENCODE_R_INT_ACK_BIT;
	#define ACK_IMGDMA_VIDEO_ENCODE_W_INT			REG_IMGDMA_INT_ACK = IMGDMA_VIDEO_ENCODE_W_INT_ACK_BIT;
	#define ACK_IMGDMA_JPEG_INT						REG_IMGDMA_INT_ACK = IMGDMA_JPEG_INT_ACK_BIT;

	/* register definition of JPEG image DMA */
	#define IMGDMA_JPEG_START_REG						(IMGDMA_base + 0x0100)
	#define IMGDMA_JPEG_CTRL_REG						(IMGDMA_base + 0x0104)
	#define IMGDMA_JPEG_BASE_ADDR_REG				(IMGDMA_base + 0x0108)
	#define IMGDMA_JPEG_WIDTH_REG						(IMGDMA_base + 0x010C)
	#define IMGDMA_JPEG_HEIGHT_REG					(IMGDMA_base + 0x0110)
	#define IMGDMA_JPEG_FIFO_LENGTH_REG				(IMGDMA_base + 0x0114)

	#define REG_IMGDMA_JPEG_START						*((volatile unsigned int *)(IMGDMA_base + 0x0100))
	#define REG_IMGDMA_JPEG_CTRL						*((volatile unsigned int *)(IMGDMA_base + 0x0104))
	#define REG_IMGDMA_JPEG_BASE_ADDR				*((volatile unsigned int *)(IMGDMA_base + 0x0108))
	#define REG_IMGDMA_JPEG_WIDTH						*((volatile unsigned int *)(IMGDMA_base + 0x010C))
	#define REG_IMGDMA_JPEG_HEIGHT					*((volatile unsigned int *)(IMGDMA_base + 0x0110))
	#define REG_IMGDMA_JPEG_FIFO_LENGTH				*((volatile unsigned int *)(IMGDMA_base + 0x0114))

	/* bit mapping of JPEG image dma control register */
	#define IMGDMA_JPEG_PIXEL_SRC_SEL_BIT			0x00000080
	#define IMGDMA_JPEG_AUTO_RESTART_BIT			0x00000008
	#define IMGDMA_JPEG_DATA_FORMAT_MASK			0x00000006
	#define IMGDMA_JPEG_INT_ENABLE_BIT				0x00000001

	#define IMGDMA_JPEG_FORMAT_YUV422				0x00000000
	#define IMGDMA_JPEG_FORMAT_GRAY					0x00000002
	#define IMGDMA_JPEG_FORMAT_YUV420				0x00000004

	#define IMGDMA_JPEG_SRC_CRZ						0x00000000
	#define IMGDMA_JPEG_SRC_PRZ						0x00000080

	/* macros of JPEG image DMA start register */
	#define START_IMGDMA_JPEG							REG_IMGDMA_JPEG_START=1;
	#define STOP_IMGDMA_JPEG							REG_IMGDMA_JPEG_START=0;

	/* macros of JPEG image DMA control register */
	#define SET_IMGDMA_JPEG_SRC_CRZ					REG_IMGDMA_JPEG_CTRL &= ~IMGDMA_JPEG_PIXEL_SRC_SEL_BIT;
	#define SET_IMGDMA_JPEG_SRC_PRZ					REG_IMGDMA_JPEG_CTRL |= IMGDMA_JPEG_PIXEL_SRC_SEL_BIT;
	#define ENABLE_IMGDMA_JPEG_AUTO_RESTART		REG_IMGDMA_JPEG_CTRL |= IMGDMA_JPEG_AUTO_RESTART_BIT;
	#define DISABLE_IMGDMA_JPEG_AUTO_RESTART		REG_IMGDMA_JPEG_CTRL &= ~IMGDMA_JPEG_AUTO_RESTART_BIT;
	#define SET_IMGDMA_JPEG_YUV422					REG_IMGDMA_JPEG_CTRL &= ~IMGDMA_JPEG_DATA_FORMAT_MASK;
	#define SET_IMGDMA_JPEG_YUV420					REG_IMGDMA_JPEG_CTRL &= ~IMGDMA_JPEG_DATA_FORMAT_MASK;\
																REG_IMGDMA_JPEG_CTRL |= IMGDMA_JPEG_FORMAT_YUV420;
	#define SET_IMGDMA_JPEG_GRAY						REG_IMGDMA_JPEG_CTRL &= ~IMGDMA_JPEG_DATA_FORMAT_MASK;\
																REG_IMGDMA_JPEG_CTRL |= IMGDMA_JPEG_FORMAT_GRAY;
	#define ENABLE_IMGDMA_JPEG_INT					REG_IMGDMA_JPEG_CTRL |= IMGDMA_JPEG_INT_ENABLE_BIT;
	#define DISABLE_IMGDMA_JPEG_INT					REG_IMGDMA_JPEG_CTRL &= ~IMGDMA_JPEG_INT_ENABLE_BIT;

	/* register definition of video encode image DMA */
	#define IMGDMA_VIDEO_ENCODE_START_REG			(IMGDMA_base + 0x0200)
	#define IMGDMA_VIDEO_ENCODE_CTRL_REG			(IMGDMA_base + 0x0204)
	#define IMGDMA_VIDEO_ENCODE_Y_BASE_ADDR1_REG	(IMGDMA_base + 0x0210)
	#define IMGDMA_VIDEO_ENCODE_U_BASE_ADDR1_REG	(IMGDMA_base + 0x0214)
	#define IMGDMA_VIDEO_ENCODE_V_BASE_ADDR1_REG	(IMGDMA_base + 0x0218)
	#define IMGDMA_VIDEO_ENCODE_Y_BASE_ADDR2_REG	(IMGDMA_base + 0x0220)
	#define IMGDMA_VIDEO_ENCODE_U_BASE_ADDR2_REG	(IMGDMA_base + 0x0224)
	#define IMGDMA_VIDEO_ENCODE_V_BASE_ADDR2_REG	(IMGDMA_base + 0x0228)
	#define IMGDMA_VIDEO_ENCODE_WIDTH_REG			(IMGDMA_base + 0x0230)
	#define IMGDMA_VIDEO_ENCODE_HEIGHT_REG			(IMGDMA_base + 0x0234)

	#define REG_IMGDMA_VIDEO_ENCODE_START			*((volatile unsigned int *)(IMGDMA_base + 0x0200))
	#define REG_IMGDMA_VIDEO_ENCODE_CTRL			*((volatile unsigned int *)(IMGDMA_base + 0x0204))
	#define REG_IMGDMA_VIDEO_ENCODE_Y_BASE_ADDR1	*((volatile unsigned int *)(IMGDMA_base + 0x0210))
	#define REG_IMGDMA_VIDEO_ENCODE_U_BASE_ADDR1	*((volatile unsigned int *)(IMGDMA_base + 0x0214))
	#define REG_IMGDMA_VIDEO_ENCODE_V_BASE_ADDR1	*((volatile unsigned int *)(IMGDMA_base + 0x0218))
	#define REG_IMGDMA_VIDEO_ENCODE_Y_BASE_ADDR2	*((volatile unsigned int *)(IMGDMA_base + 0x0220))
	#define REG_IMGDMA_VIDEO_ENCODE_U_BASE_ADDR2	*((volatile unsigned int *)(IMGDMA_base + 0x0224))
	#define REG_IMGDMA_VIDEO_ENCODE_V_BASE_ADDR2	*((volatile unsigned int *)(IMGDMA_base + 0x0228))
	#define REG_IMGDMA_VIDEO_ENCODE_WIDTH			*((volatile unsigned int *)(IMGDMA_base + 0x0230))
	#define REG_IMGDMA_VIDEO_ENCODE_HEIGHT			*((volatile unsigned int *)(IMGDMA_base + 0x0234))

	/* bit mapping of video encode image dma control register */
	#define IMGDMA_VIDEO_ENCODE_W_PIXEL_SRC_BIT	0x00000080
	#define IMGDMA_VIDEO_ENCODE_R_PIXEL_DEST_BIT	0x00000040
	#define IMGDMA_VIDEO_ENCODE_AUTO_RESTART_BIT	0x00000010
	#define IMGDMA_VIDEO_ENCODE_R_INT_BIT			0x00000008
	#define IMGDMA_VIDEO_ENCODE_W_TRIGGER_R_BIT	0x00000004
	#define IMGDMA_VIDEO_ENCODE_W_INT_BIT			0x00000001

	/* macros of Video encode image DMA start register */
	#define START_IMGDMA_VIDEO_ENCODE				REG_IMGDMA_VIDEO_ENCODE_START=1;
	#define STOP_IMGDMA_VIDEO_ENCODE					REG_IMGDMA_VIDEO_ENCODE_START=0;

	/* macros of video encode image dma control register */
	#define SET_VIDEO_ENCODE_SRC_CRZ					REG_IMGDMA_VIDEO_ENCODE_CTRL &= ~IMGDMA_VIDEO_ENCODE_W_PIXEL_SRC_BIT;
	#define SET_VIDEO_ENCODE_SRC_PRZ					REG_IMGDMA_VIDEO_ENCODE_CTRL |= IMGDMA_VIDEO_ENCODE_W_PIXEL_SRC_BIT;
	#define SET_VIDEO_ENCODE_R_DEST_PRZ				REG_IMGDMA_VIDEO_ENCODE_CTRL &= ~IMGDMA_VIDEO_ENCODE_R_PIXEL_DEST_BIT;
	#define SET_VIDEO_ENCODE_R_DEST_DRZ				REG_IMGDMA_VIDEO_ENCODE_CTRL |= IMGDMA_VIDEO_ENCODE_R_PIXEL_DEST_BIT;
	#define ENABLE_VIDEO_ENCODE_AUTO_RESTART		REG_IMGDMA_VIDEO_ENCODE_CTRL |= IMGDMA_VIDEO_ENCODE_AUTO_RESTART_BIT;
	#define DISABLE_VIDEO_ENCODE_AUTO_RESTART		REG_IMGDMA_VIDEO_ENCODE_CTRL &= ~IMGDMA_VIDEO_ENCODE_AUTO_RESTART_BIT;
	#define ENABLE_VIDEO_ENCODE_R_INT				REG_IMGDMA_VIDEO_ENCODE_CTRL |= IMGDMA_VIDEO_ENCODE_R_INT_BIT;
	#define DISABLE_VIDEO_ENCODE_R_INT				REG_IMGDMA_VIDEO_ENCODE_CTRL &= ~IMGDMA_VIDEO_ENCODE_R_INT_BIT;
	#define ENABLE_VIDEO_ENCODE_W_TRIGGER_R		REG_IMGDMA_VIDEO_ENCODE_CTRL |= IMGDMA_VIDEO_ENCODE_W_TRIGGER_R_BIT;
	#define DISABLE_VIDEO_ENCODE_W_TRIGGER_R		REG_IMGDMA_VIDEO_ENCODE_CTRL &= ~IMGDMA_VIDEO_ENCODE_W_TRIGGER_R_BIT;
	#define ENABLE_VIDEO_ENCODE_W_INT				REG_IMGDMA_VIDEO_ENCODE_CTRL |= IMGDMA_VIDEO_ENCODE_W_INT_BIT;
	#define DISABLE_VIDEO_ENCODE_W_INT				REG_IMGDMA_VIDEO_ENCODE_CTRL &= ~IMGDMA_VIDEO_ENCODE_W_INT_BIT;