target.c

USB 通信,使用的是Freescale公司的CMX协议栈

/***************************************************************************
 *
 *            Copyright (c) 2006 by CMX Systems, Inc.
 *
 * This software is copyrighted by and is the sole property of
 * CMX.  All rights, title, ownership, or other interests
 * in the software remain the property of CMX.  This
 * software may only be used in accordance with the corresponding
 * license agreement.  Any unauthorized use, duplication, transmission,
 * distribution, or disclosure of this software is expressly forbidden.
 *
 * This Copyright notice may not be removed or modified without prior
 * written consent of CMX.
 *
 * CMX reserves the right to modify this software without notice.
 *
 * CMX Systems, Inc.
 * 12276 San Jose Blvd. #511
 * Jacksonville, FL 32223
 * USA
 *
 * Tel:  [phone]
 * Fax:  [phone]
 * http: www.cmx.com
 * email: [e-mail]
 *
 ***************************************************************************/
#include "target.h"
#include "hcc_types.h"
#include "mcf5222x_reg.h"

extern hcc_u32 VECTOR_TABLE[];

/* These are defined in mcf5xxx_lo.s */
int asm_set_ipl (hcc_u32 val);
void mcf5xxx_wr_cacr (hcc_u32 val);
void mcf5xxx_wr_vbr (hcc_u32 val);

void init_scm(void);
void init_ints(void);
void init_board(void);

static void init_cpu()
{
	/* Disable Software Watchdog Timer */
	MCF_SCM_CWCR = 0;

	/* Enable debug */
	MCF_GPIO_PDDPAR = 0x0F;

	/* Turn Instruction Cache ON */
	mcf5xxx_wr_cacr(0
		| MCF5XXX_CACR_CENB
		| MCF5XXX_CACR_CINV
		| MCF5XXX_CACR_DISD
		| MCF5XXX_CACR_CEIB
		| MCF5XXX_CACR_CLNF_00);
}

static void init_clock()
{
  MCF_CLOCK_CCHR =0x05; /* The PLL pre divider - 48MHz / 6 = 8MHz*/

  /* The PLL pre-divider affects this!!! Multiply 8Mhz reference crystal /CCHR
     by 10 to acheive system clock of 80Mhz */
  MCF_CLOCK_SYNCR = MCF_CLOCK_SYNCR_MFD(3) | MCF_CLOCK_SYNCR_CLKSRC
                      | MCF_CLOCK_SYNCR_PLLMODE | MCF_CLOCK_SYNCR_PLLEN ;
  while (!(MCF_CLOCK_SYNSR & MCF_CLOCK_SYNSR_LOCK))
    ;

}

void init_scm()
{
volatile int a=0;
  /* Enable on-chip modules to access internal SRAM */
  MCF_SCM_RAMBAR = (0
    | MCF_SCM_RAMBAR_BA(SRAM_ADDRESS)
    | MCF_SCM_RAMBAR_BDE);
}

void init_ints()
{
  /* Set base address of vector table. */
  mcf5xxx_wr_vbr((hcc_u32)VECTOR_TABLE);
}

void init_board(void)
{
  /* Setup leds. */
  /* Enable signals as GPIO */
  MCF_GPIO_PTCPAR = 0
        | MCF_GPIO_PTCPAR_TIN3_GPIO
        | MCF_GPIO_PTCPAR_TIN2_GPIO
        | MCF_GPIO_PTCPAR_TIN1_GPIO
        | MCF_GPIO_PTCPAR_TIN0_GPIO;

  MCF_GPIO_PORTTC = 0x00; /* Turn LEDS off. */
    
    /* Enable signals as digital outputs */
  MCF_GPIO_DDRTC = 0
        | MCF_GPIO_DDRTC_DDRTC3
        | MCF_GPIO_DDRTC_DDRTC2
        | MCF_GPIO_DDRTC_DDRTC1
        | MCF_GPIO_DDRTC_DDRTC0;
  /* Configure switches. */  
  /* by default I/O pins are configured for input -> do nothing */
  
}

void _irq_restore (hcc_imask ip)
{
    asm_set_ipl(ip);
}

hcc_imask _irq_disable (void)
{
    return((hcc_imask)asm_set_ipl(7));
}



/********************************************************************/
void iic_delay(void)
{
	volatile hcc_u16 i;
	/* Wait for a bit */
	i=500;
	while(i--)
	;
}

void I2Cinit(void)
{
	hcc_u8 temp;
	
	/* Enable the I2C signals */
	MCF_GPIO_PASPAR |= ( MCF_GPIO_PASPAR_SDA_SDA
							 | MCF_GPIO_PASPAR_SCL_SCL);
							 
	/* set the frequency near 400KHz, see MCF52223RM table for details */ 
	MCF_I2C_I2FDR = MCF_I2C_I2FDR_IC(0x32);
	/* start the module */
	MCF_I2C_I2CR = 0 | MCF_I2C_I2CR_IEN;
	
	/* if bit busy set, send a stop condition to slave module */
	if( MCF_I2C_I2SR & MCF_I2C_I2SR_IBB)
	{
		MCF_I2C_I2CR = 0;						/* clear control register */
		MCF_I2C_I2CR = MCF_I2C_I2CR_IEN |		/* enable module */
					   MCF_I2C_I2CR_MSTA;		/* send a START conditionn */
		temp = MCF_I2C_I2DR;					/* dummy read */
		MCF_I2C_I2SR = 0;						/* clear status register */
		MCF_I2C_I2CR = 0;						/* clear control register */
		MCF_I2C_I2CR = 0 | MCF_I2C_I2CR_IEN;	/* enable the module again */
	}
	return;	
}

hcc_u8 I2CreceiveByte(hcc_u8 address, hcc_u8 id)
{
	hcc_u8 data;
	
	MCF_I2C_I2CR |= MCF_I2C_I2CR_MTX;			/* setting in Tx mode */
	/* send start condition */
	MCF_I2C_I2CR |= MCF_I2C_I2CR_MSTA;
	MCF_I2C_I2DR = id;							/* devide ID to write */
	/* wait until one byte transfer completion */
	while( !(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF ))
	;
	/* clear the completion transfer flag */
	MCF_I2C_I2SR &= ~MCF_I2C_I2SR_IIF;
	MCF_I2C_I2DR = address;						/* memory address */
	/* wait until one byte transfer completion */
	while( !(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF ))
	;
	/* clear the completion transfer flag */
	MCF_I2C_I2SR &= ~MCF_I2C_I2SR_IIF;	 	
	MCF_I2C_I2CR |= MCF_I2C_I2CR_RSTA;			/* resend start */
	MCF_I2C_I2DR = (hcc_u8)(id | 0x01);					/* device id to read */
	/* wait until one byte transfer completion */
	while( !(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF ))
	;
	/* clear the completion transfer flag */
	MCF_I2C_I2SR &= ~MCF_I2C_I2SR_IIF;
	MCF_I2C_I2CR &= ~MCF_I2C_I2CR_MTX;			/* setting in Rx mode */
	MCF_I2C_I2CR |= MCF_I2C_I2CR_TXAK;			/* send NO ACK */
	data = MCF_I2C_I2DR;						/* dummy read */
	/* wait until one byte transfer completion */
	while( !(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF ))
	;
	/* clear the completion transfer flag */
	MCF_I2C_I2SR &= ~MCF_I2C_I2SR_IIF;
	data = MCF_I2C_I2DR;						/* read data received */
	/* wait until one byte transfer completion */
	while( !(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF ))
	;
	/* clear the completion transfer flag */
	MCF_I2C_I2SR &= ~MCF_I2C_I2SR_IIF;
	/* generates stop condition */
	MCF_I2C_I2CR &= ~MCF_I2C_I2CR_MSTA;
	/* send the received data */
	return data;
}

void I2CsendByte(int data, int address, int id)
{
	MCF_I2C_I2CR |= MCF_I2C_I2CR_MTX;			/* setting in Tx mode */
	/* generates start condition */
	MCF_I2C_I2CR |= MCF_I2C_I2CR_MSTA;
	MCF_I2C_I2DR = (hcc_u8)id;							/* set devide ID to write */
	/* wait until one byte transfer completion */
	while( !(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF ))
	;
	/* clear the completion transfer flag */
	MCF_I2C_I2SR &= ~MCF_I2C_I2SR_IIF;
	MCF_I2C_I2DR =(hcc_u8)address;						/* memory address */
	iic_delay();
	/* wait until one byte transfer completion */
	while( !(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF ))
	;
	/* clear the completion transfer flag */
	MCF_I2C_I2SR &= ~MCF_I2C_I2SR_IIF;	
	MCF_I2C_I2DR = (hcc_u8)data;						/* memory data */
	/* wait until one byte transfer completion */
	iic_delay();
	while( !(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF ))
	;
	/* clear the completion transfer flag */
	MCF_I2C_I2SR &= ~MCF_I2C_I2SR_IIF;	
	/* generates stop condition */
	MCF_I2C_I2CR &= ~MCF_I2C_I2CR_MSTA;
	return;
}


void hw_init(void)
{
  init_cpu();
  init_clock();
  init_board();
  init_scm();
  init_ints();
  I2Cinit();
  _irq_restore(0);
}