mcf5222x_reg.h

USB 通信,使用的是Freescale公司的CMX协议栈

#define MCF_INTC_IPRH_INT37        (0x00000020)
#define MCF_INTC_IPRH_INT38        (0x00000040)
#define MCF_INTC_IPRH_INT39        (0x00000080)
#define MCF_INTC_IPRH_INT40        (0x00000100)
#define MCF_INTC_IPRH_INT41        (0x00000200)
#define MCF_INTC_IPRH_INT42        (0x00000400)
#define MCF_INTC_IPRH_INT43        (0x00000800)
#define MCF_INTC_IPRH_INT44        (0x00001000)
#define MCF_INTC_IPRH_INT45        (0x00002000)
#define MCF_INTC_IPRH_INT46        (0x00004000)
#define MCF_INTC_IPRH_INT47        (0x00008000)
#define MCF_INTC_IPRH_INT48        (0x00010000)
#define MCF_INTC_IPRH_INT49        (0x00020000)
#define MCF_INTC_IPRH_INT50        (0x00040000)
#define MCF_INTC_IPRH_INT51        (0x00080000)
#define MCF_INTC_IPRH_INT52        (0x00100000)
#define MCF_INTC_IPRH_INT53        (0x00200000)
#define MCF_INTC_IPRH_INT54        (0x00400000)
#define MCF_INTC_IPRH_INT55        (0x00800000)
#define MCF_INTC_IPRH_INT56        (0x01000000)
#define MCF_INTC_IPRH_INT57        (0x02000000)
#define MCF_INTC_IPRH_INT58        (0x04000000)
#define MCF_INTC_IPRH_INT59        (0x08000000)
#define MCF_INTC_IPRH_INT60        (0x10000000)
#define MCF_INTC_IPRH_INT61        (0x20000000)
#define MCF_INTC_IPRH_INT62        (0x40000000)
#define MCF_INTC_IPRH_INT63        (0x80000000)

/* Bit definitions and macros for MCF_INTC_IPRL */
#define MCF_INTC_IPRL_INT1         (0x00000002)
#define MCF_INTC_IPRL_INT2         (0x00000004)
#define MCF_INTC_IPRL_INT3         (0x00000008)
#define MCF_INTC_IPRL_INT4         (0x00000010)
#define MCF_INTC_IPRL_INT5         (0x00000020)
#define MCF_INTC_IPRL_INT6         (0x00000040)
#define MCF_INTC_IPRL_INT7         (0x00000080)
#define MCF_INTC_IPRL_INT8         (0x00000100)
#define MCF_INTC_IPRL_INT9         (0x00000200)
#define MCF_INTC_IPRL_INT10        (0x00000400)
#define MCF_INTC_IPRL_INT11        (0x00000800)
#define MCF_INTC_IPRL_INT12        (0x00001000)
#define MCF_INTC_IPRL_INT13        (0x00002000)
#define MCF_INTC_IPRL_INT14        (0x00004000)
#define MCF_INTC_IPRL_INT15        (0x00008000)
#define MCF_INTC_IPRL_INT16        (0x00010000)
#define MCF_INTC_IPRL_INT17        (0x00020000)
#define MCF_INTC_IPRL_INT18        (0x00040000)
#define MCF_INTC_IPRL_INT19        (0x00080000)
#define MCF_INTC_IPRL_INT20        (0x00100000)
#define MCF_INTC_IPRL_INT21        (0x00200000)
#define MCF_INTC_IPRL_INT22        (0x00400000)
#define MCF_INTC_IPRL_INT23        (0x00800000)
#define MCF_INTC_IPRL_INT24        (0x01000000)
#define MCF_INTC_IPRL_INT25        (0x02000000)
#define MCF_INTC_IPRL_INT26        (0x04000000)
#define MCF_INTC_IPRL_INT27        (0x08000000)
#define MCF_INTC_IPRL_INT28        (0x10000000)
#define MCF_INTC_IPRL_INT29        (0x20000000)
#define MCF_INTC_IPRL_INT30        (0x40000000)
#define MCF_INTC_IPRL_INT31        (0x80000000)

/* Bit definitions and macros for MCF_INTC_IMRH */
#define MCF_INTC_IMRH_MASK32       (0x00000001)
#define MCF_INTC_IMRH_MASK33       (0x00000002)
#define MCF_INTC_IMRH_MASK34       (0x00000004)
#define MCF_INTC_IMRH_MASK35       (0x00000008)
#define MCF_INTC_IMRH_MASK36       (0x00000010)
#define MCF_INTC_IMRH_MASK37       (0x00000020)
#define MCF_INTC_IMRH_MASK38       (0x00000040)
#define MCF_INTC_IMRH_MASK39       (0x00000080)
#define MCF_INTC_IMRH_MASK40       (0x00000100)
#define MCF_INTC_IMRH_MASK41       (0x00000200)
#define MCF_INTC_IMRH_MASK42       (0x00000400)
#define MCF_INTC_IMRH_MASK43       (0x00000800)
#define MCF_INTC_IMRH_MASK44       (0x00001000)
#define MCF_INTC_IMRH_MASK45       (0x00002000)
#define MCF_INTC_IMRH_MASK46       (0x00004000)
#define MCF_INTC_IMRH_MASK47       (0x00008000)
#define MCF_INTC_IMRH_MASK48       (0x00010000)
#define MCF_INTC_IMRH_MASK49       (0x00020000)
#define MCF_INTC_IMRH_MASK50       (0x00040000)
#define MCF_INTC_IMRH_MASK51       (0x00080000)
#define MCF_INTC_IMRH_MASK52       (0x00100000)
#define MCF_INTC_IMRH_MASK53       (0x00200000)
#define MCF_INTC_IMRH_MASK54       (0x00400000)
#define MCF_INTC_IMRH_MASK55       (0x00800000)
#define MCF_INTC_IMRH_MASK56       (0x01000000)
#define MCF_INTC_IMRH_MASK57       (0x02000000)
#define MCF_INTC_IMRH_MASK58       (0x04000000)
#define MCF_INTC_IMRH_MASK59       (0x08000000)
#define MCF_INTC_IMRH_MASK60       (0x10000000)
#define MCF_INTC_IMRH_MASK61       (0x20000000)
#define MCF_INTC_IMRH_MASK62       (0x40000000)
#define MCF_INTC_IMRH_MASK63       (0x80000000)

/* Bit definitions and macros for MCF_INTC_IMRL */
#define MCF_INTC_IMRL_MASKALL      (0x00000001)
#define MCF_INTC_IMRL_MASK1        (0x00000002)
#define MCF_INTC_IMRL_MASK2        (0x00000004)
#define MCF_INTC_IMRL_MASK3        (0x00000008)
#define MCF_INTC_IMRL_MASK4        (0x00000010)
#define MCF_INTC_IMRL_MASK5        (0x00000020)
#define MCF_INTC_IMRL_MASK6        (0x00000040)
#define MCF_INTC_IMRL_MASK7        (0x00000080)
#define MCF_INTC_IMRL_MASK8        (0x00000100)
#define MCF_INTC_IMRL_MASK9        (0x00000200)
#define MCF_INTC_IMRL_MASK10       (0x00000400)
#define MCF_INTC_IMRL_MASK11       (0x00000800)
#define MCF_INTC_IMRL_MASK12       (0x00001000)
#define MCF_INTC_IMRL_MASK13       (0x00002000)
#define MCF_INTC_IMRL_MASK14       (0x00004000)
#define MCF_INTC_IMRL_MASK15       (0x00008000)
#define MCF_INTC_IMRL_MASK16       (0x00010000)
#define MCF_INTC_IMRL_MASK17       (0x00020000)
#define MCF_INTC_IMRL_MASK18       (0x00040000)
#define MCF_INTC_IMRL_MASK19       (0x00080000)
#define MCF_INTC_IMRL_MASK20       (0x00100000)
#define MCF_INTC_IMRL_MASK21       (0x00200000)
#define MCF_INTC_IMRL_MASK22       (0x00400000)
#define MCF_INTC_IMRL_MASK23       (0x00800000)
#define MCF_INTC_IMRL_MASK24       (0x01000000)
#define MCF_INTC_IMRL_MASK25       (0x02000000)
#define MCF_INTC_IMRL_MASK26       (0x04000000)
#define MCF_INTC_IMRL_MASK27       (0x08000000)
#define MCF_INTC_IMRL_MASK28       (0x10000000)
#define MCF_INTC_IMRL_MASK29       (0x20000000)
#define MCF_INTC_IMRL_MASK30       (0x40000000)
#define MCF_INTC_IMRL_MASK31       (0x80000000)

/* Bit definitions and macros for MCF_INTC_INTFRCH */
#define MCF_INTC_INTFRCH_INTFRC32  (0x00000001)
#define MCF_INTC_INTFRCH_INTFRC33  (0x00000002)
#define MCF_INTC_INTFRCH_INTFRC34  (0x00000004)
#define MCF_INTC_INTFRCH_INTFRC35  (0x00000008)
#define MCF_INTC_INTFRCH_INTFRC36  (0x00000010)
#define MCF_INTC_INTFRCH_INTFRC37  (0x00000020)
#define MCF_INTC_INTFRCH_INTFRC38  (0x00000040)
#define MCF_INTC_INTFRCH_INTFRC39  (0x00000080)
#define MCF_INTC_INTFRCH_INTFRC40  (0x00000100)
#define MCF_INTC_INTFRCH_INTFRC41  (0x00000200)
#define MCF_INTC_INTFRCH_INTFRC42  (0x00000400)
#define MCF_INTC_INTFRCH_INTFRC43  (0x00000800)
#define MCF_INTC_INTFRCH_INTFRC44  (0x00001000)
#define MCF_INTC_INTFRCH_INTFRC45  (0x00002000)
#define MCF_INTC_INTFRCH_INTFRC46  (0x00004000)
#define MCF_INTC_INTFRCH_INTFRC47  (0x00008000)
#define MCF_INTC_INTFRCH_INTFRC48  (0x00010000)
#define MCF_INTC_INTFRCH_INTFRC49  (0x00020000)
#define MCF_INTC_INTFRCH_INTFRC50  (0x00040000)
#define MCF_INTC_INTFRCH_INTFRC51  (0x00080000)
#define MCF_INTC_INTFRCH_INTFRC52  (0x00100000)
#define MCF_INTC_INTFRCH_INTFRC53  (0x00200000)
#define MCF_INTC_INTFRCH_INTFRC54  (0x00400000)
#define MCF_INTC_INTFRCH_INTFRC55  (0x00800000)
#define MCF_INTC_INTFRCH_INTFRC56  (0x01000000)
#define MCF_INTC_INTFRCH_INTFRC57  (0x02000000)
#define MCF_INTC_INTFRCH_INTFRC58  (0x04000000)
#define MCF_INTC_INTFRCH_INTFRC59  (0x08000000)
#define MCF_INTC_INTFRCH_INTFRC60  (0x10000000)
#define MCF_INTC_INTFRCH_INTFRC61  (0x20000000)
#define MCF_INTC_INTFRCH_INTFRC62  (0x40000000)
#define MCF_INTC_INTFRCH_INTFRC63  (0x80000000)

/* Bit definitions and macros for MCF_INTC_INTFRCL */
#define MCF_INTC_INTFRCL_INTFRC1   (0x00000002)
#define MCF_INTC_INTFRCL_INTFRC2   (0x00000004)
#define MCF_INTC_INTFRCL_INTFRC3   (0x00000008)
#define MCF_INTC_INTFRCL_INTFRC4   (0x00000010)
#define MCF_INTC_INTFRCL_INTFRC5   (0x00000020)
#define MCF_INTC_INTFRCL_INTFRC6   (0x00000040)
#define MCF_INTC_INTFRCL_INTFRC7   (0x00000080)
#define MCF_INTC_INTFRCL_INTFRC8   (0x00000100)
#define MCF_INTC_INTFRCL_INTFRC9   (0x00000200)
#define MCF_INTC_INTFRCL_INTFRC10  (0x00000400)
#define MCF_INTC_INTFRCL_INTFRC11  (0x00000800)
#define MCF_INTC_INTFRCL_INTFRC12  (0x00001000)
#define MCF_INTC_INTFRCL_INTFRC13  (0x00002000)
#define MCF_INTC_INTFRCL_INTFRC14  (0x00004000)
#define MCF_INTC_INTFRCL_INTFRC15  (0x00008000)
#define MCF_INTC_INTFRCL_INTFRC16  (0x00010000)
#define MCF_INTC_INTFRCL_INTFRC17  (0x00020000)
#define MCF_INTC_INTFRCL_INTFRC18  (0x00040000)
#define MCF_INTC_INTFRCL_INTFRC19  (0x00080000)
#define MCF_INTC_INTFRCL_INTFRC20  (0x00100000)
#define MCF_INTC_INTFRCL_INTFRC21  (0x00200000)
#define MCF_INTC_INTFRCL_INTFRC22  (0x00400000)
#define MCF_INTC_INTFRCL_INTFRC23  (0x00800000)
#define MCF_INTC_INTFRCL_INTFRC24  (0x01000000)
#define MCF_INTC_INTFRCL_INTFRC25  (0x02000000)
#define MCF_INTC_INTFRCL_INTFRC26  (0x04000000)
#define MCF_INTC_INTFRCL_INTFRC27  (0x08000000)
#define MCF_INTC_INTFRCL_INTFRC28  (0x10000000)
#define MCF_INTC_INTFRCL_INTFRC29  (0x20000000)
#define MCF_INTC_INTFRCL_INTFRC30  (0x40000000)
#define MCF_INTC_INTFRCL_INTFRC31  (0x80000000)

/* Bit definitions and macros for MCF_INTC_IRLR */
#define MCF_INTC_IRLR_IRQ(x)       (((x)&0x7F)<<1)

/* Bit definitions and macros for MCF_INTC_IACKLPR */
#define MCF_INTC_IACKLPR_PRI(x)    (((x)&0x0F)<<0)
#define MCF_INTC_IACKLPR_LEVEL(x)  (((x)&0x07)<<4)

/* Bit definitions and macros for MCF_INTC_ICR */
#define MCF_INTC_ICR_IP(x)         (((x)&0x07)<<0)
#define MCF_INTC_ICR_IL(x)         (((x)&0x07)<<3)

/* Bit definitions and macros for MCF_INTC_SWIACK */
#define MCF_INTC_SWIACK_VECTOR(x)  (((x)&0xFF)<<0)

/* Bit definitions and macros for MCF_INTC_LIACK */
#define MCF_INTC_LIACK_VECTOR(x)   (((x)&0xFF)<<0)

/*********************************************************************
*
* General Purpose I/O (GPIO)
*
*********************************************************************/

/* Register read/write macros */
#define MCF_GPIO_PORTNQ                   (*(hcc_reg8 *)(&_IPSBAR[0x100008]))
#define MCF_GPIO_PORTAN                   (*(hcc_reg8 *)(&_IPSBAR[0x10000A]))
#define MCF_GPIO_PORTAS                   (*(hcc_reg8 *)(&_IPSBAR[0x10000B]))
#define MCF_GPIO_PORTQS                   (*(hcc_reg8 *)(&_IPSBAR[0x10000C]))
#define MCF_GPIO_PORTTA                   (*(hcc_reg8 *)(&_IPSBAR[0x10000E]))
#define MCF_GPIO_PORTTC                   (*(hcc_reg8 *)(&_IPSBAR[0x10000F]))
#define MCF_GPIO_PORTUA                   (*(hcc_reg8 *)(&_IPSBAR[0x100011]))
#define MCF_GPIO_PORTUB                   (*(hcc_reg8 *)(&_IPSBAR[0x100012]))
#define MCF_GPIO_PORTUC                   (*(hcc_reg8 *)(&_IPSBAR[0x100013]))
#define MCF_GPIO_PORTDD                   (*(hcc_reg8 *)(&_IPSBAR[0x100014]))
#define MCF_GPIO_DDRNQ                    (*(hcc_reg8 *)(&_IPSBAR[0x100020]))
#define MCF_GPIO_DDRAN                    (*(hcc_reg8 *)(&_IPSBAR[0x100022]))
#define MCF_GPIO_DDRAS                    (*(hcc_reg8 *)(&_IPSBAR[0x100023]))
#define MCF_GPIO_DDRQS                    (*(hcc_reg8 *)(&_IPSBAR[0x100024]))
#define MCF_GPIO_DDRTA                    (*(hcc_reg8 *)(&_IPSBAR[0x100026]))
#define MCF_GPIO_DDRTC                    (*(hcc_reg8 *)(&_IPSBAR[0x100027]))
#define MCF_GPIO_DDRUA                    (*(hcc_reg8 *)(&_IPSBAR[0x100029]))
#define MCF_GPIO_DDRUB                    (*(hcc_reg8 *)(&_IPSBAR[0x10002A]))
#define MCF_GPIO_DDRUC                    (*(hcc_reg8 *)(&_IPSBAR[0x10002B]))
#define MCF_GPIO_DDRDD                    (*(hcc_reg8 *)(&_IPSBAR[0x10002C]))
#define MCF_GPIO_SETNQ                    (*(hcc_reg8 *)(&_IPSBAR[0x100038]))
#define MCF_GPIO_SETAN                    (*(hcc_reg8 *)(&_IPSBAR[0x10003A]))
#define MCF_GPIO_SETAS                    (*(hcc_reg8 *)(&_IPSBAR[0x10003B]))
#define MCF_GPIO_SETQS                    (*(hcc_reg8 *)(&_IPSBAR[0x10003C]))
#define MCF_GPIO_SETTA                    (*(hcc_reg8 *)(&_IPSBAR[0x10003E]))
#define MCF_GPIO_SETTC                    (*(hcc_reg8 *)(&_IPSBAR[0x10003F]))
#define MCF_GPIO_SETUA                    (*(hcc_reg8 *)(&_IPSBAR[0x100041]))
#define MCF_GPIO_SETUB                    (*(hcc_reg8 *)(&_IPSBAR[0x100042]))
#define MCF_GPIO_SETUC                    (*(hcc_reg8 *)(&_IPSBAR[0x100043]))
#define MCF_GPIO_SETDD                    (*(hcc_reg8 *)(&_IPSBAR[0x100044]))
#define MCF_GPIO_CLRNQ                    (*(hcc_reg8 *)(&_IPSBAR[0x100050]))
#define MCF_GPIO_CLRAN                    (*(hc