mcf5222x_reg.h

USB 通信,使用的是Freescale公司的CMX协议栈

/***************************************************************************
 *
 *            Copyright (c) 2006 by CMX Systems, Inc.
 *
 * This software is copyrighted by and is the sole property of
 * CMX.  All rights, title, ownership, or other interests
 * in the software remain the property of CMX.  This
 * software may only be used in accordance with the corresponding
 * license agreement.  Any unauthorized use, duplication, transmission,
 * distribution, or disclosure of this software is expressly forbidden.
 *
 * This Copyright notice may not be removed or modified without prior
 * written consent of CMX.
 *
 * CMX reserves the right to modify this software without notice.
 *
 * CMX Systems, Inc.
 * 12276 San Jose Blvd. #511
 * Jacksonville, FL 32223
 * USA
 *
 * Tel:  [phone]
 * Fax:  [phone]
 * http: www.cmx.com
 * email: [e-mail]
 *
 ***************************************************************************/
#ifndef _MCF5222X_REGS_H_
#define _MCF5222X_REGS_H_

#include "hcc_types.h"

/* 
 * Memory map definitions from linker command files 
 */
extern hcc_u8 _IPSBAR[];
extern hcc_u32 _SRAM[];

/* 
 * Memory Map Info 
 */
#define IPSBAR_ADDRESS			(hcc_u32)_IPSBAR

#define SRAM_ADDRESS			(hcc_u32)_SRAM

#define BITX(x) (1U<<##x)
#define BIT0	BITX(0)
#define BIT1	BITX(1)
#define BIT2	BITX(2)
#define BIT3	BITX(3)
#define BIT4	BITX(4)
#define BIT5	BITX(5)
#define BIT6	BITX(6)
#define BIT7 	BITX(7)
#define BIT8	BITX(8)
#define BIT9	BITX(9)
#define BIT10   BITX(10)
#define BIT11	BITX(11)
#define BIT12   BITX(12)
#define BIT13	BITX(13)
#define BIT14   BITX(14)
#define BIT15	BITX(15)
#define BIT16   BITX(16)
#define BIT17	BITX(17)
#define BIT18   BITX(18)
#define BIT19	BITX(19)
#define BIT20   BITX(20)
#define BIT21	BITX(21)
#define BIT22   BITX(22)
#define BIT23	BITX(23)
#define BIT24   BITX(24)
#define BIT25	BITX(25)
#define BIT26   BITX(26)
#define BIT27	BITX(27)
#define BIT28   BITX(28)
#define BIT29	BITX(29)
#define BIT30   BITX(30)
#define BIT31	BITX(31)

/*********************************************************************
*
* Core register bit definitions
*
*********************************************************************/
/* Status Register */
#define MCF5XXX_SR_T        (0x8000)
#define MCF5XXX_SR_S        (0x2000)
#define MCF5XXX_SR_M        (0x1000)
#define MCF5XXX_SR_IPL      (0x0700)
#define MCF5XXX_SR_IPL_0    (0x0000)
#define MCF5XXX_SR_IPL_1    (0x0100)
#define MCF5XXX_SR_IPL_2    (0x0200)
#define MCF5XXX_SR_IPL_3    (0x0300)
#define MCF5XXX_SR_IPL_4    (0x0400)
#define MCF5XXX_SR_IPL_5    (0x0500)
#define MCF5XXX_SR_IPL_6    (0x0600)
#define MCF5XXX_SR_IPL_7    (0x0700)
#define MCF5XXX_SR_X        (0x0010)
#define MCF5XXX_SR_N        (0x0008)
#define MCF5XXX_SR_Z        (0x0004)
#define MCF5XXX_SR_V        (0x0002)
#define MCF5XXX_SR_C        (0x0001)

/* Cache Control Register */
#define MCF5XXX_CACR_CENB       (0x80000000)
#define MCF5XXX_CACR_DEC        (0x80000000)
#define MCF5XXX_CACR_DW         (0x40000000)
#define MCF5XXX_CACR_DESB       (0x20000000)
#define MCF5XXX_CACR_CPDI       (0x10000000)
#define MCF5XXX_CACR_DDPI       (0x10000000)
#define MCF5XXX_CACR_CPD        (0x10000000)
#define MCF5XXX_CACR_CFRZ       (0x08000000)
#define MCF5XXX_CACR_DHLCK      (0x08000000)
#define MCF5XXX_CACR_DDCM_WT    (0x00000000)
#define MCF5XXX_CACR_DDCM_CB    (0x02000000)
#define MCF5XXX_CACR_DDCM_IP    (0x04000000)
#define MCF5XXX_CACR_DDCM_II    (0x06000000)
#define MCF5XXX_CACR_CINV       (0x01000000)
#define MCF5XXX_CACR_DCINVA     (0x01000000)
#define MCF5XXX_CACR_DIDI       (0x00800000)
#define MCF5XXX_CACR_DDSP       (0x00800000)
#define MCF5XXX_CACR_DISD       (0x00400000)
#define MCF5XXX_CACR_INVI       (0x00200000)
#define MCF5XXX_CACR_INVD       (0x00100000)
#define MCF5XXX_CACR_BEC        (0x00080000)
#define MCF5XXX_CACR_BCINVA     (0x00040000)
#define MCF5XXX_CACR_IEC        (0x00008000)
#define MCF5XXX_CACR_DNFB       (0x00002000)
#define MCF5XXX_CACR_IDPI       (0x00001000)
#define MCF5XXX_CACR_IHLCK      (0x00000800)
#define MCF5XXX_CACR_CEIB       (0x00000400)
#define MCF5XXX_CACR_IDCM       (0x00000400)
#define MCF5XXX_CACR_DCM_WR     (0x00000000)
#define MCF5XXX_CACR_DCM_CB     (0x00000100)
#define MCF5XXX_CACR_DCM_IP     (0x00000200)
#define MCF5XXX_CACR_DCM        (0x00000200)
#define MCF5XXX_CACR_DCM_II     (0x00000300)
#define MCF5XXX_CACR_DBWE       (0x00000100)
#define MCF5XXX_CACR_ICINVA     (0x00000100)
#define MCF5XXX_CACR_IDSP       (0x00000080)
#define MCF5XXX_CACR_DWP        (0x00000020)
#define MCF5XXX_CACR_EUSP       (0x00000020)
#define MCF5XXX_CACR_EUST       (0x00000020)
#define MCF5XXX_CACR_DF         (0x00000010)
#define MCF5XXX_CACR_CLNF_00    (0x00000000)
#define MCF5XXX_CACR_CLNF_01    (0x00000002)
#define MCF5XXX_CACR_CLNF_10    (0x00000004)
#define MCF5XXX_CACR_CLNF_11    (0x00000006)

/* Access Control Register */
#define MCF5XXX_ACR_AB(a)       ((a)&0xFF000000)
#define MCF5XXX_ACR_AM(a)       (((a)&0xFF000000) >> 8)
#define MCF5XXX_ACR_AM_4G       (0x00FF0000)
#define MCF5XXX_ACR_AM_2G       (0x007F0000)
#define MCF5XXX_ACR_AM_1G       (0x003F0000)
#define MCF5XXX_ACR_AM_1024M    (0x003F0000)
#define MCF5XXX_ACR_AM_512M     (0x001F0000)
#define MCF5XXX_ACR_AM_256M     (0x000F0000)
#define MCF5XXX_ACR_AM_128M     (0x00070000)
#define MCF5XXX_ACR_AM_64M      (0x00030000)
#define MCF5XXX_ACR_AM_32M      (0x00010000)
#define MCF5XXX_ACR_AM_16M      (0x00000000)
#define MCF5XXX_ACR_EN          (0x00008000)
#define MCF5XXX_ACR_SM_USER     (0x00000000)
#define MCF5XXX_ACR_SM_SUPER    (0x00002000)
#define MCF5XXX_ACR_SM_IGNORE   (0x00006000)
#define MCF5XXX_ACR_ENIB        (0x00000080)
#define MCF5XXX_ACR_CM          (0x00000040)
#define MCF5XXX_ACR_DCM_WR      (0x00000000)
#define MCF5XXX_ACR_DCM_CB      (0x00000020)
#define MCF5XXX_ACR_DCM_IP      (0x00000040)
#define MCF5XXX_ACR_DCM_II      (0x00000060)
#define MCF5XXX_ACR_CM          (0x00000040)
#define MCF5XXX_ACR_BWE         (0x00000020)
#define MCF5XXX_ACR_WP          (0x00000004)

/* RAM Base Address Register */
#define MCF5XXX_RAMBAR_BA(a)    ((a)&0xFFFFC000)
#define MCF5XXX_RAMBAR_PRI_00   (0x00000000)
#define MCF5XXX_RAMBAR_PRI_01   (0x00004000)
#define MCF5XXX_RAMBAR_PRI_10   (0x00008000)
#define MCF5XXX_RAMBAR_PRI_11   (0x0000C000)
#define MCF5XXX_RAMBAR_WP       (0x00000100)
#define MCF5XXX_RAMBAR_CI       (0x00000020)
#define MCF5XXX_RAMBAR_SC       (0x00000010)
#define MCF5XXX_RAMBAR_SD       (0x00000008)
#define MCF5XXX_RAMBAR_UC       (0x00000004)
#define MCF5XXX_RAMBAR_UD       (0x00000002)
#define MCF5XXX_RAMBAR_V        (0x00000001)

/*********************************************************************
*
* System Control Module (SCM)
*
*********************************************************************/

/* Register read/write macros */
#define MCF_SCM_IPSBAR               (*(hcc_reg32*)(&_IPSBAR[0x000000]))
#define MCF_SCM_RAMBAR               (*(hcc_reg32*)(&_IPSBAR[0x000008]))
#define MCF_SCM_CRSR                 (*(hcc_reg8 *)(&_IPSBAR[0x000010]))
#define MCF_SCM_CWCR                 (*(hcc_reg8 *)(&_IPSBAR[0x000011]))
#define MCF_SCM_LPICR                (*(hcc_reg8 *)(&_IPSBAR[0x000012]))
#define MCF_SCM_CWSR                 (*(hcc_reg8 *)(&_IPSBAR[0x000013]))
#define MCF_SCM_PPMRH                (*(hcc_reg32*)(&_IPSBAR[0x00000C]))
#define MCF_SCM_PPMRL                (*(hcc_reg32*)(&_IPSBAR[0x000018]))
#define MCF_SCM_PPMRS                (*(hcc_reg8 *)(&_IPSBAR[0x000021]))
#define MCF_SCM_PPMRC                (*(hcc_reg8 *)(&_IPSBAR[0x000022]))

/* Bit definitions and macros for MCF_SCM_IPSBAR */
#define MCF_SCM_IPSBAR_V             (0x00000001)
#define MCF_SCM_IPSBAR_BA(x)         ((x)&0xC0000000)

/* Bit definitions and macros for MCF_SCM_RAMBAR */
#define MCF_SCM_RAMBAR_BDE           (0x00000200)
#define MCF_SCM_RAMBAR_BA(x)         ((x)&0xFFFF0000)

/* Bit definitions and macros for MCF_SCM_CRSR */
#define MCF_SCM_CRSR_CWDR            (0x20)
#define MCF_SCM_CRSR_EXT             (0x80)

/* Bit definitions and macros for MCF_SCM_CWCR */
#define MCF_SCM_CWCR_CWTIC           (0x01)
#define MCF_SCM_CWCR_CWTAVAL         (0x02)
#define MCF_SCM_CWCR_CWTA            (0x04)
#define MCF_SCM_CWCR_CWT(x)          (((x)&0x07)<<3)
#define MCF_SCM_CWCR_CWRI            (0x40)
#define MCF_SCM_CWCR_CWE             (0x80)

/* Bit definitions and macros for MCF_SCM_LPICR */
#define MCF_SCM_LPICR_XIPL(x)        (((x)&0x07)<<4)
#define MCF_SCM_LPICR_ENBSTOP        (0x80)

/* Bit definitions and macros for MCF_SCM_CWSR */
#define MCF_SCM_CWSR_CWSR(x)         (((x)&0xFF)<<0)

/* Bit definitions and macros for MCF_SCM_PPMRH */
#define MCF_SCM_PPMRH_CDPORTS        (0x00000001)
#define MCF_SCM_PPMRH_CDEPORT        (0x00000002)
#define MCF_SCM_PPMRH_CDPIT0         (0x00000008)
#define MCF_SCM_PPMRH_CDPIT1         (0x00000010)
#define MCF_SCM_PPMRH_CDADC          (0x00000080)
#define MCF_SCM_PPMRH_CDGPT          (0x00000100)
#define MCF_SCM_PPMRH_CDPWN          (0x00000200)
#define MCF_SCM_PPMRH_CDFCAN         (0x00000400)
#define MCF_SCM_PPMRH_CDCFM          (0x00000800)

/* Bit definitions and macros for MCF_SCM_PPMRL */
#define MCF_SCM_PPMRL_CDG            (0x00000002)
#define MCF_SCM_PPMRL_CDEIM          (0x00000008)
#define MCF_SCM_PPMRL_CDDMA          (0x00000010)
#define MCF_SCM_PPMRL_CDUART0        (0x00000020)
#define MCF_SCM_PPMRL_CDUART1        (0x00000040)
#define MCF_SCM_PPMRL_CDUART2        (0x00000080)
#define MCF_SCM_PPMRL_CDI2C          (0x00000200)