📄 msdma.c
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if (DRCHOST(usbRegDevCtl))
{
usbREG_WRITE8(USB_REG_RXCSR2,(csr2 | RXCSR2_MODE1 | M_RXCSR2_H_AUTOREQ));
pbWriteUSB16RegINT((__u16)(DMA_CNTL_REGISTER(ch)), control);
}
else
{
usbREG_WRITE8(USB_REG_RXCSR2, (csr2 | RXCSR2_MODE1));
if(OtgDeviceType==Device_MassStorage)
{
pbWriteUSB16Reg(USB_REG_DMA_MODE_CTL, (pbReadUSB16Reg(USB_REG_DMA_MODE_CTL)&M_Mode1_P_Enable));
//printf("speed=%bx\n",usbSpeed);
if(usbSpeed == HIGH_SPEED)
pbWriteUSB16Reg(USB_REG_DMA_MODE_CTL, (pbReadUSB16Reg(USB_REG_DMA_MODE_CTL)|(count/512))); //disable set_ok2rcv[15]&ECO4NAK_en[14],wayne added
else
pbWriteUSB16Reg(USB_REG_DMA_MODE_CTL, (pbReadUSB16Reg(USB_REG_DMA_MODE_CTL)|(count/64))); //disable set_ok2rcv[15]&ECO4NAK_en[14],wayne added
pbWriteUSB16Reg(USB_REG_DMA_MODE_CTL, (pbReadUSB16Reg(USB_REG_DMA_MODE_CTL)|M_Mode1_P_OK2Rcv)); //enable set_ok2rcv[15]&ECO4NAK_en[14],wayne added
pbWriteUSB16Reg(USB_REG_DMA_MODE_CTL, (pbReadUSB16Reg(USB_REG_DMA_MODE_CTL)&(~M_Mode1_P_OK2Rcv))); //enable set_ok2rcv[15]&ECO4NAK_en[14],wayne added
usbREG_WRITE8(USB_REG_RXCSR1, 0);//enable RX
}
printf("MCTLINT=%x\n",pbReadUSB16Reg(USB_REG_DMA_MODE_CTL));
//pbWriteUSB16RegINT((__u16)(DMA_CNTL_REGISTER(ch)), control);
#ifdef USB_DEBUG
//printf("\r\nRXCSR2 = %x ",usbREG_READ8(USB_REG_RXCSR2));
#endif
//usbREG_WRITE8(USB_REG_RXCSR1, 0);//enable RX
}
/* restore previous index value */
//usbREG_WRITE8(USB_REG_INDEX, index);
//pbWriteUSB16Reg((__u16)(DMA_CNTL_REGISTER(ch)), control);
return SUCCESS;
case DMA_TX | DMA_MODE_ONE:
#ifdef Artemis_DEBUG
printf("\r\n Act TX_DMA", 0);//artemis printf
#endif
Enable_TX_EP_InterruptINT(ep);
csr2 = usbREG_READ8(USB_REG_TXCSR2);
usbREG_WRITE8(USB_REG_TXCSR2, (csr2 | TXCSR2_MODE1));
break;
#ifdef USB_DEBUG
//printf("\r\nTXCSR2 = %x ",usbREG_READ8(USB_REG_TXCSR2));
#endif
}
/* restore previous index value */
usbREG_WRITE8(USB_REG_INDEX, index);
#ifdef BIG_ENDIAN
pbWriteUSB16RegINT((__u16)(DMA_CNTL_REGISTER(ch)), control);
#else
*(DMA_CNTL_REGISTER(ch)) = control;
#endif
return SUCCESS;
}
#ifdef BIG_ENDIAN
void USB_DMA_IRQ_Handler(__u8 ch)
{
__u8 index, endpoint, direction;
__u32 bytesleft;
__u8 csr2, csr;
__u8 mode, control;
//printf("\r\n C1",0);
/* get DMA Mode, address and byte counts from DMA registers */
control = usbREG_READ8((__u16)DMA_CNTL_REGISTER(ch));
mode = usbREG_READ8((__u16)DMA_CNTL_REGISTER(ch))&0x0f;
//addr = *(DMA_ADDR_REGISTER(ch));
bytesleft=usbREG_READ8((__u16)DMA_COUNT_REGISTER(ch));
/* get endpoint, URB pointer */
if(EPConfig&0x10)
{
direction = (mode & DMA_TX) ? 0 : 1;
endpoint= usb_Ret_Blt_EP_Object(direction);
//printf("\r\n D_d=%x",direction);
//printf("\r\n D_E=%x",endpoint);
}
else
{
endpoint = (usbREG_READ8((__u16)DMA_CNTL_REGISTER(ch))&0xf0) >> DMA_ENDPOINT_SHIFT;
direction = (mode & DMA_TX) ? 0 : 1;
}
#ifdef USB_DEBUG
//printf("\r\ncontrol = %x ",control);
//printf("\r\nmode = %x ",mode);
//printf("\r\nInt_bleft = %x ",bytesleft);
//printf("\r\nInt_bleft2 = %x ",(__u16)(bytesleft>>16));
//printf("\r\nInt_ep = %x ",endpoint);
#endif
/* how many bytes were processed ? */
//bytesdone = addr -usbXdataSDRAMBaseAddr- (__u32)(usbEP[endpoint].transfer_buffer + usbEP[endpoint].BytesProcessed);
usbEP[endpoint].BytesProcessed = usbEP[endpoint].BytesRequested;
/* save and set index register */
index = usbREG_READ8(USB_REG_INDEX);
if(EPConfig&0x10)
usbREG_WRITE8(USB_REG_INDEX, usbEP[endpoint].BltEP2);
else
usbREG_WRITE8(USB_REG_INDEX, usbEP[endpoint].BltEP);
/* release DMA channel */
Release_DMA_Channel(ch);
/* clean DMA setup in CSR */
if (mode & DMA_TX)
{
csr2 = usbREG_READ8(USB_REG_TXCSR2);
usbREG_WRITE8(USB_REG_TXCSR2, (csr2 & ~TXCSR2_MODE1));
}
else
{
csr2 = usbREG_READ8(USB_REG_RXCSR2);
if (DRCHOST(usbRegDevCtl))
usbREG_WRITE8(USB_REG_RXCSR2,(csr2 & ~(RXCSR2_MODE1 | M_RXCSR2_H_AUTOREQ)));
else
usbREG_WRITE8(USB_REG_RXCSR2, (csr2 & ~RXCSR2_MODE1));
}
/* Bus Error */
if (control & DMA_BUSERROR_BIT)
{
//usbIntStatus=USB_ST_STALL;
if (endpoint==0x3)
usbIntInStatus=USB_ST_STALL;
else if (endpoint==0x01)
usbBulkInStatus=USB_ST_STALL;
else
usbBulkOutStatus=USB_ST_STALL;
return;
}
if (mode & DMA_TX)
{
//printf("\r\n DmaTxHand",0);//artemis printf
//printf("\r\n DTx",0);//artemis printf
IntCheck--;
if (usbEP[endpoint].BytesProcessed == usbEP[endpoint].BytesRequested)
{
if (usbEP[endpoint].BytesProcessed % usbEP[endpoint].MaxEPSize) /* short packet */
{
usbEP[endpoint].LastPacket = 1; /* need to set TXPKTRDY manually */
}
else /* the last packet size is equal to MaxEPSize */
{
if (mode & (DMA_MODE_ONE))
{
usbEP[endpoint].LastPacket = 1;
//usbIntStatus=USB_ST_NOERROR;
if (endpoint==0x3)
usbIntInStatus=USB_ST_NOERROR;
else
{
if(usbIsPeripheral())
usbBulkInStatus2=USB_ST_NOERROR;
else
usbBulkInStatus=USB_ST_NOERROR;
}
return;
}
else
{
if (usb_pipebulk(usbDataPhaseDir))
usbEP[endpoint].LastPacket = 1;
}
}
}
}
else
{
//#ifdef Artemis_DEBUG
//printf("\r\n DmaRxHand",0);//artemis printf
//#endif
Enable_RX_EP_InterruptINT(endpoint);
usbEP[endpoint].FifoRemain = bytesleft;
if (usbEP[endpoint].FifoRemain == 0)
{
if (usbEP[endpoint].BytesProcessed % usbEP[endpoint].MaxEPSize) /* short packet */
{
usbEP[endpoint].LastPacket = 1;
}
else /* the last packet size is equal to MaxEPSize */
{
if (mode & DMA_MODE_ONE)
{
usbEP[endpoint].LastPacket = 1;
//usbIntStatus=USB_ST_NOERROR;
usbBulkOutStatus=USB_ST_NOERROR;
return;
}
}
}
}
/* for short packet, CPU needs to handle TXPKTRDY/RXPKTRDY bit */
if (mode & DMA_TX)
{
usbREG_WRITE8(USB_REG_TXCSR1, M_TXCSR1_TXPKTRDY);
}
else
{
csr = usbREG_READ8(USB_REG_RXCSR1);
usbREG_WRITE8(USB_REG_RXCSR1, (csr & ~M_RXCSR1_RXPKTRDY));
}
/* restore the index */
usbREG_WRITE8(USB_REG_INDEX, index);
if (mode & DMA_TX)
return;
else
{
if (((!usbEP[endpoint].FifoRemain) && (usbEP[endpoint].LastPacket)) || (usbEP[endpoint].BytesProcessed >= usbEP[endpoint].BytesRequested))
{
//usbIntStatus=USB_ST_NOERROR;
usbBulkOutStatus=USB_ST_NOERROR;
}
}
}
#else
void USB_DMA_IRQ_Handler(__u8 ch)
{
__u8 index, endpoint, direction;
__u32 bytesleft, addr, bytesdone;
__u8 csr2, csr;
__u16 mode, control;
/* get DMA Mode, address and byte counts from DMA registers */
control = *(DMA_CNTL_REGISTER(ch));
mode = *(DMA_CNTL_REGISTER(ch)) & 0xf;
addr = *(DMA_ADDR_REGISTER(ch));
bytesleft = *(DMA_COUNT_REGISTER(ch));
/* get endpoint, URB pointer */
endpoint = (*(DMA_CNTL_REGISTER(ch)) & 0xf0) >> DMA_ENDPOINT_SHIFT;
direction = (mode & DMA_TX) ? 0 : 1;
/* how many bytes were processed ? */
bytesdone = addr -usbXdataSDRAMBaseAddr- (__u32)(usbEP[endpoint].transfer_buffer + usbEP[endpoint].BytesProcessed);
usbEP[endpoint].BytesProcessed += bytesdone;
/* save and set index register */
index = usbREG_READ8(USB_REG_INDEX);
usbREG_WRITE8(USB_REG_INDEX, usbEP[endpoint].BltEP);
/* release DMA channel */
Release_DMA_Channel(ch);
/* clean DMA setup in CSR */
if (mode & DMA_TX)
{
csr2 = usbREG_READ8(USB_REG_TXCSR2);
usbREG_WRITE8(USB_REG_TXCSR2, (csr2 & ~TXCSR2_MODE1));
}
else
{
csr2 = usbREG_READ8(USB_REG_RXCSR2);
if (DRCHOST(usbRegDevCtl))
usbREG_WRITE8(USB_REG_RXCSR2,(csr2 & ~(RXCSR2_MODE1 | M_RXCSR2_H_AUTOREQ)));
else
usbREG_WRITE8(USB_REG_RXCSR2, (csr2 & ~RXCSR2_MODE1));
}
/* Bus Error */
if (control & DMA_BUSERROR_BIT)
{
usbIntStatus=USB_ST_STALL;
return;
}
if (mode & DMA_TX)
{
if (usbEP[endpoint].BytesProcessed == usbEP[endpoint].BytesRequested)
{
if (usbEP[endpoint].BytesProcessed % usbEP[endpoint].MaxEPSize) /* short packet */
{
usbEP[endpoint].LastPacket = 1; /* need to set TXPKTRDY manually */
}
else /* the last packet size is equal to MaxEPSize */
{
if (mode & (DMA_MODE_ONE))
{
usbEP[endpoint].LastPacket = 1;
usbIntStatus=USB_ST_NOERROR;
return;
}
else
{
if (usb_pipebulk(usbDataPhaseDir))
usbEP[endpoint].LastPacket = 1;
}
}
}
}
else
{
Enable_RX_EP_Interrupt(endpoint);
usbEP[endpoint].FifoRemain = bytesleft;
if (usbEP[endpoint].FifoRemain == 0)
{
if (usbEP[endpoint].BytesProcessed % usbEP[endpoint].MaxEPSize) /* short packet */
{
usbEP[endpoint].LastPacket = 1;
}
else /* the last packet size is equal to MaxEPSize */
{
if (mode & DMA_MODE_ONE)
{
usbEP[endpoint].LastPacket = 1;
usbIntStatus=USB_ST_NOERROR;
return;
}
}
}
}
/* for short packet, CPU needs to handle TXPKTRDY/RXPKTRDY bit */
if (mode & DMA_TX)
{
usbREG_WRITE8(USB_REG_TXCSR1, M_TXCSR1_TXPKTRDY);
}
else
{
csr = usbREG_READ8(USB_REG_RXCSR1);
usbREG_WRITE8(USB_REG_RXCSR1, (csr & ~M_RXCSR1_RXPKTRDY));
}
/* restore the index */
usbREG_WRITE8(USB_REG_INDEX, index);
if (mode & DMA_TX)
return;
else
{
if (((!usbEP[endpoint].FifoRemain) && (usbEP[endpoint].LastPacket)) || (usbEP[endpoint].BytesProcessed >= usbEP[endpoint].BytesRequested))
{
usbIntStatus=USB_ST_NOERROR;
}
}
}
#endif
#if 0
void usbDisable_DMA(__s8 channel)
{
__u16 control;
control = *(DMA_CNTL_REGISTER(channel));
control &= (__u16)~DMA_ENABLE_BIT;
*(DMA_CNTL_REGISTER(channel)) = control;
}
__u16 usbRead_DMA_Control(__s8 channel)
{
return *((DMA_CNTL_REGISTER(channel)));
}
#endif
void Control_EP_Interrupt(__s8 ep, __u16 mode)
{
__u8 reg, current, tbit;
__u8 endpoint;
if(EPConfig&0x10)
endpoint = usbEP[ep].BltEP2;
else
endpoint = usbEP[ep].BltEP;
if(mode & EP_IRQ_TX)
reg = (endpoint < 8) ? USB_REG_INTRTX1E : USB_REG_INTRTX2E;
else
reg = (endpoint < 8) ? USB_REG_INTRRX1E : USB_REG_INTRRX2E;
current = usbREG_READ8(reg);
tbit = 1 << (endpoint % 8);
if(mode & EP_IRQ_ENABLE)
usbREG_WRITE8(reg, (current | tbit));
else
usbREG_WRITE8(reg, (current & ~tbit));
}
void Control_EP_InterruptINT(__s8 ep, __u16 mode)
{
__u8 reg, current, tbit;
__u8 endpoint;
if(EPConfig&0x10)
endpoint = usbEP[ep].BltEP2;
else
endpoint = usbEP[ep].BltEP;
if(mode & EP_IRQ_TX)
reg = (endpoint < 8) ? USB_REG_INTRTX1E : USB_REG_INTRTX2E;
else
reg = (endpoint < 8) ? USB_REG_INTRRX1E : USB_REG_INTRRX2E;
current = usbREG_READ8(reg);
tbit = 1 << (endpoint % 8);
if(mode & EP_IRQ_ENABLE)
usbREG_WRITE8(reg, (current | tbit));
else
usbREG_WRITE8(reg, (current & ~tbit));
}⌨️ 快捷键说明
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