📄 msdrc.h
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#ifndef __MSDRC_H_
#define __MSDRC_H_
#ifndef _Indirect
#define usbREG_READ8(r) (DRC_IN8(usbRegAddress + (r)))
#else
__u8 usbREG_READ8(__u16 addr);
#endif
#define usbREG_WRITE8(r,v) (DRC_OUT8(usbRegAddress + (r),(v)))
#define usbREG_READ16(r) (DRC_IN16(usbRegAddress + (r)))
#define usbREG_WRITE16(r,v) (DRC_OUT16(usbRegAddress + (r),(v)))
#if 1
#define usbEXTREG_READ8(r) (DRC_IN8(usbEXTRegAddress + (r)))
#define usbEXTREG_WRITE8(r,v) (DRC_OUT8(usbEXTRegAddress + (r),(v)))
#define usbREG_READ32(r) (DRC_IN32(usbRegAddress + (r)))
#define usbREG_WRITE32(r,v) (DRC_OUT32(usbRegAddress + (r),(v)))
#endif
#define Swap16(val) ((val<<8) | (val>>8))
#define VBUS_BELOW_SESSION_END 0
#define VBUS_ABOVE_SESSION_END 1
#define VBUS_ABOVE_AVALID 2
#define VBUS_ABOVE_VBUS_VALID 3
#define VBUS_ERROR 256
//////////////////////////////////////////////////////////////////
#define USB_REG_FADDR (0x00<<OffShift) /* 8 bit */
#define USB_REG_POWER (0x01<<OffShift) /* 8 bit */
#define USB_REG_INTRTX (0x02<<OffShift)
#define USB_REG_INTRRX (0x04<<OffShift)
#define USB_REG_INTRTXE (0x06<<OffShift)
#define USB_REG_INTRRXE (0x08<<OffShift)
#define USB_REG_INTRUSB (0x0A<<OffShift) /* 8 bit */
#define USB_REG_INTRUSBE (0x0B<<OffShift) /* 8 bit */
#define USB_REG_FRAME (0x0C<<OffShift)
#define USB_REG_INDEX (0x0E<<OffShift) /* 8 bit */
#define USB_REG_TESTMODE (0x0F<<OffShift) /* 8 bit */
#define USB_REG_TARGET_FUNCTION_BASE (0x80<<OffShift) /* 8 bit */
#define USB_REG_TXMAXP (0x10<<OffShift)
#define USB_REG_CSR0 (0x12<<OffShift)
#define USB_REG_TXCSR (0x12<<OffShift)
#define USB_REG_RXMAXP (0x14<<OffShift)
#define USB_REG_RXCSR (0x16<<OffShift)
#define USB_REG_COUNT0 (0x18<<OffShift)
#define USB_REG_RXCOUNT (0x18<<OffShift)
#define USB_REG_TXTYPE (0x1A<<OffShift) /* 8 bit, only valid in Host mode */
#define USB_REG_TYPE0 (0x1A<<OffShift) /* 2 bit, only valid in MDRC Host mode */
#define REG_NAKLIMIT0 (0x1B<<OffShift) /* 8 bit, only valid in Host mode */
#define USB_REG_TXINTERVAL (0x1B<<OffShift) /* 8 bit, only valid in Host mode */
#define USB_REG_RXTYPE (0x1C<<OffShift) /* 8 bit, only valid in Host mode */
#define USB_REG_RXINTERVAL (0x1D<<OffShift) /* 8 bit, only valid in Host mode */
#define USB_REG_CONFIGDATA (0x1F<<OffShift) /* 8 bit */
#define USB_REG_FIFOSIZE (0x1F<<OffShift) /* 8 bit */
/* FIFOs for Endpoints 0 - 15, 32 bit word boundaries */
#define M_FIFO_EP0 (0x20<<OffShift)
#define REG_DEVCTL (0x60<<OffShift) /* 8 bit */
#define USB_REG_TXFIFOSZ (0x62<<OffShift) /* 8 bit, TxFIFO size */
#define USB_REG_RXFIFOSZ (0x63<<OffShift) /* 8 bit, RxFIFO size */
#define USB_REG_TXFIFOADD (0x64<<OffShift) /* 16 bit, TxFIFO address */
#define USB_REG_RXFIFOADD (0x66<<OffShift) /* 16 bit, RxFIFO address */
#define USB_REG_INTRTX1 (0x02<<OffShift) /* 8 bit */
#define USB_REG_INTRTX2 (0x03<<OffShift) /* 8 bit */
#define USB_REG_INTRRX1 (0x04<<OffShift) /* 8 bit */
#define USB_REG_INTRRX2 (0x05<<OffShift) /* 8 bit */
#define USB_REG_INTRTX1E (0x06<<OffShift) /* 8 bit */
#define USB_REG_INTRTX2E (0x07<<OffShift) /* 8 bit */
#define USB_REG_INTRRX1E (0x08<<OffShift) /* 8 bit */
#define USB_REG_INTRRX2E (0x09<<OffShift) /* 8 bit */
#define USB_REG_TXCSR1 (0x12<<OffShift)
#define USB_REG_TXCSR2 (0x13<<OffShift)
#define USB_REG_RXCSR1 (0x16<<OffShift)
#define USB_REG_RXCSR2 (0x17<<OffShift)
// Derek added 2008/01/10
#define USB_REG_USB_CFG0 (0x80 << OffShift)
#define USB_REG_CFG2_L (0x84 << OffShift)
#define USB_REG_EP_BULKOUT (0x86 << OffShift)
#define USB_REG_DMA_MODE_CTL (0x8A << OffShift)
/* POWER */
#define M_POWER_ISOUPDATE 0x80
#define M_POWER_SOFTCONN 0x40
#define M_POWER_HSENAB 0x20
#define M_POWER_HSMODE 0x10
#define M_POWER_RESET 0x08
#define M_POWER_RESUME 0x04
#define M_POWER_SUSPENDM 0x02
#define M_POWER_ENSUSPEND 0x01
/* TESTMODE */
#define M_TEST_FIFOACCESS 0x40
#define M_TEST_FORCEFS 0x20
#define M_TEST_FORCEHS 0x10
#define M_TEST_PACKET 0x08
#define M_TEST_K 0x04
#define M_TEST_J 0x02
#define M_TEST_SE0_NAK 0x01
/*
* High Speed Test Mode Selectors
*/
#define M_FTR_TESTJ 0x0100
#define M_FTR_TESTK 0x0200
#define M_FTR_TESTSE0 0x0300
#define M_FTR_TESTPKT 0x0400
/* DEVCTL */
#define M_DEVCTL_BDEVICE 0x80
#define M_DEVCTL_FSDEV 0x40
#define M_DEVCTL_LSDEV 0x20
#define M_DEVCTL_HM 0x04
#define M_DEVCTL_HR 0x02
#define M_DEVCTL_SESSION 0x01
/* CSR0 in Peripheral and Host mode */
#define M_CSR0_FLUSHFIFO 0x0100
#define M_CSR0_TXPKTRDY 0x0002
#define M_CSR0_RXPKTRDY 0x0001
/* CSR0 in HSFC */
#define M_CSR0_INPKTRDY 0x02
#define M_CSR0_OUTPKTRDY 0x01
/* CSR0 in Peripheral mode */
#define M_CSR0_P_SVDSETUPEND 0x0080
#define M_CSR0_P_SVDRXPKTRDY 0x0040
#define M_CSR0_P_SENDSTALL 0x0020
#define M_CSR0_P_SETUPEND 0x0010
#define M_CSR0_P_DATAEND 0x0008
#define M_CSR0_P_SENTSTALL 0x0004
/* CSR0 in Host mode */
#define M_CSR0_H_NAKTIMEOUT 0x0080
#define M_CSR0_H_STATUSPKT 0x0040
#define M_CSR0_H_REQPKT 0x0020
#define M_CSR0_H_ERROR 0x0010
#define M_CSR0_H_SETUPPKT 0x0008
#define M_CSR0_H_RXSTALL 0x0004
/* TXCSR in Peripheral and Host mode */
#define M_TXCSR_AUTOSET 0x8000
#define M_TXCSR_ISO 0x4000
#define M_TXCSR_MODE 0x2000
#define M_TXCSR_DMAENAB 0x1000
#define M_TXCSR_FRCDATATOG 0x0800
#define M_TXCSR_DMAMODE 0x0400
#define M_TXCSR_CLRDATATOG 0x0040
#define M_TXCSR_FLUSHFIFO 0x0008
#define M_TXCSR_FIFONOTEMPTY 0x0002
#define M_TXCSR_TXPKTRDY 0x0001
/* TXCSR in Peripheral mode */
#define M_TXCSR_P_INCOMPTX 0x0080
#define M_TXCSR_P_SENTSTALL 0x0020
#define M_TXCSR_P_SENDSTALL 0x0010
#define M_TXCSR_P_UNDERRUN 0x0004
/* TXCSR in Host mode */
#define M_TXCSR_H_NAKTIMEOUT 0x0080
#define M_TXCSR_H_RXSTALL 0x0020
#define M_TXCSR_H_ERROR 0x0004
/* RXCSR in Peripheral and Host mode */
#define M_RXCSR_AUTOCLEAR 0x8000
#define M_RXCSR_DMAENAB 0x2000
#define M_RXCSR_DISNYET 0x1000
#define M_RXCSR_DMAMODE 0x0800
#define M_RXCSR_INCOMPRX 0x0100
#define M_RXCSR_CLRDATATOG 0x0080
#define M_RXCSR_FLUSHFIFO 0x0010
#define M_RXCSR_DATAERROR 0x0008
#define M_RXCSR_FIFOFULL 0x0002
#define M_RXCSR_RXPKTRDY 0x0001
/* RXCSR in Peripheral mode */
#define M_RXCSR_P_ISO 0x4000
#define M_RXCSR_P_SENTSTALL 0x0040
#define M_RXCSR_P_SENDSTALL 0x0020
#define M_RXCSR_P_OVERRUN 0x0004
/* TXCSR in Peripheral and Host mode */
#define M_TXCSR2_AUTOSET 0x80
#define M_TXCSR2_ISO 0x40
#define M_TXCSR2_MODE 0x20
#define M_TXCSR2_DMAENAB 0x10
#define M_TXCSR2_FRCDATATOG 0x08
#define M_TXCSR2_DMAMODE 0x04
#define M_TXCSR1_CLRDATATOG 0x40
#define M_TXCSR1_FLUSHFIFO 0x08
#define M_TXCSR1_FIFONOTEMPTY 0x02
#define M_TXCSR1_TXPKTRDY 0x01
/* TXCSR in Peripheral mode */
#define M_TXCSR1_P_INCOMPTX 0x80
#define M_TXCSR1_P_SENTSTALL 0x20
#define M_TXCSR1_P_SENDSTALL 0x10
#define M_TXCSR1_P_UNDERRUN 0x04
/* TXCSR in Host mode */
#define M_TXCSR1_H_NAKTIMEOUT 0x80
#define M_TXCSR1_H_RXSTALL 0x20
#define M_TXCSR1_H_ERROR 0x04
/* RXCSR in Peripheral and Host mode */
#define M_RXCSR2_AUTOCLEAR 0x80
#define M_RXCSR2_DMAENAB 0x20
#define M_RXCSR2_DISNYET 0x10
#define M_RXCSR2_DMAMODE 0x08
#define M_RXCSR2_INCOMPRX 0x01
#define M_RXCSR1_CLRDATATOG 0x80
#define M_RXCSR1_FLUSHFIFO 0x10
#define M_RXCSR1_DATAERROR 0x08
#define M_RXCSR1_FIFOFULL 0x02
#define M_RXCSR1_RXPKTRDY 0x01
/* RXCSR in Peripheral mode */
#define M_RXCSR2_P_ISO 0x40
#define M_RXCSR1_P_SENTSTALL 0x40
#define M_RXCSR1_P_SENDSTALL 0x20
#define M_RXCSR1_P_OVERRUN 0x04
/* RXCSR in Host mode */
#define M_RXCSR2_H_AUTOREQ 0x40
#define M_RXCSR1_H_RXSTALL 0x40
#define M_RXCSR1_H_REQPKT 0x20
#define M_RXCSR1_H_ERROR 0x04
#define PIPE_CONTROL 0
#define PIPE_ISOCHRONOUS 1
#define PIPE_BULK 2
#define PIPE_INTERRUPT 3
#define PIPE_IN 1 /* direction */
#define PIPE_OUT 0
#define PIPEDEF_DIR 7 /* 1 is IN, 0 is OUT */
#define PIPEDEF_ATTR 4 /* 00=Control,01=ISO,10=BULK,11=INT */
#define PIPEDEF_EP 0 /* endpoints 1 - 15 */
#ifdef BIG_ENDIAN
#define usbRead_RxCount() usbREG_READ8(USB_REG_RXCOUNT);
#else
#define usbRead_RxCount() usbREG_READ16(USB_REG_RXCOUNT);
#endif
#define VBUS_MASK 0x18 /* DevCtl D4 - D3 */
/* reg_usb_cfg0 */
#define reg_usb_cfg0_srstn 0x0001
/* new mode1 in Peripheral mode */
#define M_Mode1_P_BulkOut_EP 0x0002
#define M_Mode1_P_OK2Rcv 0x8000
#define M_Mode1_P_AllowAck 0x4000
#define M_Mode1_P_Enable 0x2000
//#ifndef MIN(a,b)
//#define MIN(a,b) (((a) < (b)) ? (a) : (b))
//#endif
#define A_DEVICE() (usbcid == CID_A_DEVICE)
#define B_DEVICE() (usbcid == CID_B_DEVICE)
typedef struct
{
__u16 FIFOSize;
__u16 MaxEPSize;
__u16 FifoRemain;
__u32 BytesRequested;
__u32 BytesProcessed;
__u8 DRCInterval;
__u8 intr_flag;
__u8 pipe;
__u8 BltEP;
__u8 DRCDir;
__u8 LastPacket;
__u8 IOState;
__u8 Halted;
__u8 Infnum;
__s32 transfer_buffer;
__s32 transfer_buffer_length;
__u8 BltEP2;
} endpoint_t;
#define FIFO_TX 0 /* endpoint fifo is TX only */
#define FIFO_RX 1 /* endpoint fifo is RX only */
#define FIFO_DUAL 2 /* endpoint fifo is TX or RX */
#define FIFO_DPB 16 /* double packet buffering */
#define FIFO_ERROR 256
typedef struct
{
__u16 IReg; /* holds content of INTRUSB|CSR0|TXCSR1|RXCSR1 */
__u16 ICount; /* 8-bit COUNT holds bits 0-7 for RX EP */
__u8 IIntSrc; /* 0=TXInt,1=Rxint for EP interrupts */
__u8 ICause; /* 0=INTRUSB, 1=EP */
__u8 InUse; /* 0=free,1=holds interrupt data */
__u8 IDMA; /* set if DMA interrupt */
__u8 IDummy; /* unclaimed,use at will */
__u8 IEP; /* identifies the EP when EP is source of int */
} drcintitem_t;
#define IRC_INTRUSB 0 /* 2 possible cause codes:INTRUSB ... */
#define IRC_EP 1 /* or an endpoint */
extern endpoint_t volatile usbEP[];
extern struct devrequest usbEP0Setup;
extern __s8 volatile usbResetting;
extern __s8 volatile usbRegPower;
extern __u8 volatile usbUSBStatus;
extern __u8 volatile usbIntStatus;
extern __u8 volatile usbIntInStatus;
extern __u8 volatile usbBulkInStatus;
extern __u8 volatile usbBulkOutStatus;
extern __u8 volatile usbDataPhaseDir;
extern __u8 volatile GetPartHeaderTransfer;
extern __u8 volatile usbBulkInStatus2;
//extern __u8 volatile usbPictCmdRevFlag;
extern __u8 volatile usbPictRxDataReceived;
extern __u32 volatile USB_TTX_FIX_XDATA_ADDR;
void usbRead_DRC_Power(void);
void usbRead_DRC_Devctl(void);
void usbParse_DRC_Int(drcintitem_t *dP);
void usbReset_DRC_Core(void);
void usbSet_DRC_Power(__u8 regupdate);
void usbClear_DRC_Power( __u8 regupdate);
void usbRefresh_DRC_Registers(void);
void usbSet_DRC_Devctl(__u8 regupdate);
void usbClear_DRC_Devctl(__u8 regupdate);
///////////////////////////////////////////////
void USB_Setup_Endpoint(__s8 epnum,__s8 epdir,__s8 eptype,__s8 epinf ,__s16 epmaxps);
void usbDRC_Index_Select(__u8 epnum);
void usbDRC_Index_Select_INT(__u8 epnum);
void usbReset_EP_DRC_Regs(__s8 ep);
void usbDRC_Fifo_Read(__u8 *dstP,__u8 ep);
void usbDRC_Fifo_Write(__u8 *srcP,__u8 ep);
void usbDRC_Fifo_Read_INT(__u8 *dstP,__u8 ep);
void usbDRC_Fifo_Write_INT(__u8 *srcP,__u8 ep);
void usbDRC_Interrupt(void);
void usb_ExternalIntrrupt(void);//artemis add at 03/13/2007
void usbSet_DRC_Interrupts(void);
void usbClear_DRC_Interrupts(void);
__s32 usbVBus_Status(void);
////////////////////////////////////////////////
__u8 SDRAM2USB_Bulk(__u32 txaddr,__u32 txsize);
__u8 USB2SDRAM_Bulk(__u32 rxaddr,__u32 rxsize);
__u8 USB2SDRAM_Bulk_MassStorage(__u32 rxaddr,__u32 rxsize);
__u8 SDRAM2USB_Int(__u32 txaddr,__u32 txsize);
//__u8 usb_Ret_Blt_EP_Object(__u8 drcdir);
void usbSDRAM2SDRAM(__u32 u32src, __u32 u32dst, __u32 u32len);
//void usbSDRAMCSDRAM(__u32 u32src, __u32 u32dst, __u32 u32len);
__u8 usbHost_Send_EP0Setup(__u8 *buffer);
void usbInitmemPool(int StarPoolAddr, int PoolSize);
void *usbMalloc(int size);
void usbFree(void * ptr);
void *usbMem_Set(void *s, __s32 c, int n);
void *usbMemcpy(void *s1, const void *s2, int n);
void usbSet_ClrRXMode1(void);
void usbReSet_ClrRXMode1(void);
__u8 usbCompareData(__u8 *ptr1, __u8 *ptr2, int n);
void CommC2X(__u8 xdata *Xdest,__u8 code *Csrc,__u16 size);
//void usbSDRAM2SDRAM(__u32 u32src, __u32 u32dst, __u32 u32len);
void pbWriteUSB32Reg(__u16 addr, __u32 x);
void pbWriteUSB16Reg(__u16 addr, __u16 x);
__u16 pbReadUSB16Reg(__u16 addr);
void pbWriteUSB32RegINT(__u16 addr, __u32 x);
void pbWriteUSB16RegINT(__u16 addr, __u16 x);
#ifdef VERSION_C
__u32 pbReadUSB32Reg(__u16 addr);
#endif
void usbDRCInit(void);
__u8 usb_Ret_Blt_EP_Object(__u8 drcdir); //artemis add at 03/08/2007
__u8 usbSend_TXDATA(__u32 txaddr,__u32 txsize);
__u8 usbReceive_RXDATA(__u32 rxaddr,__u32 rxsize);
void InitUSBVar(__u8 Device_Mode_Type);
void LopezUSBInit(void);
#endif //__MSDRC_H_⌨️ 快捷键说明
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