📄 cc1100.lst
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156 0x00, // FSCTRL0 Frequency synthesizer control.
157 0x10, // FREQ2 Frequency control word, high byte.
158 0xA7, // FREQ1 Frequency control word, middle byte.
159 0x62, // FREQ0 Frequency control word, low byte.
160 0xCA, // MDMCFG4 Modem configuration.
161 0x83, // MDMCFG3 Modem configuration.
162 0x83, // MDMCFG2 Modem configuration.
163 0x22, // MDMCFG1 Modem configuration.
164 0xF8, // MDMCFG0 Modem configuration.
165
166 0x00, // CHANNR Channel number.
167 0x34, // DEVIATN Modem deviation setting (when FSK modulation is enabled).
168 0x56, // FREND1 Front end RX configuration.
169 0x10, // FREND0 Front end RX configuration.
170 0x18, // MCSM0 Main Radio Control State Machine configuration.
171 0x16, // FOCCFG Frequency Offset Compensation Configuration.
172 0x6C, // BSCFG Bit synchronization Configuration.
173 0x43, // AGCCTRL2 AGC control.
174 0x40, // AGCCTRL1 AGC control.
175 0x91, // AGCCTRL0 AGC control.
C51 COMPILER V8.02 CC1100 11/02/2007 10:01:25 PAGE 4
176
177 0xA9, // FSCAL3 Frequency synthesizer calibration.
178 0x2A, // FSCAL2 Frequency synthesizer calibration.
179 0x00, // FSCAL1 Frequency synthesizer calibration.
180 0x11, // FSCAL0 Frequency synthesizer calibration.
181 0x59, // FSTEST Frequency synthesizer calibration.
182 0x81, // TEST2 Various test settings.
183 0x35, // TEST1 Various test settings.
184 0x09, // TEST0 Various test settings.
185 0x0B, // IOCFG2 GDO2 output pin configuration.
186 0x06, // IOCFG0D GDO0 output pin configuration. Refer to SmartRF?Studio User Manual for detailed p
-seudo register explanation.
187
188 0x04, // PKTCTRL1 Packet automation control.
189 0x05, // PKTCTRL0 Packet automation control.
190 0x00, // ADDR Device address.
191 0x0c // PKTLEN Packet length.
192 };
193 */
194 /*
195 // 100k E
196 const RF_SETTINGS rfSettings = {
197 0x00,
198 0x08, // FSCTRL1 Frequency synthesizer control.
199 0x00, // FSCTRL0 Frequency synthesizer control.
200 0x10, // FREQ2 Frequency control word, high byte.
201 0xA7, // FREQ1 Frequency control word, middle byte.
202 0x62, // FREQ0 Frequency control word, low byte.
203 0x5B, // MDMCFG4 Modem configuration.
204 0xF8, // MDMCFG3 Modem configuration.
205 0x03, // MDMCFG2 Modem configuration.
206 0x22, // MDMCFG1 Modem configuration.
207 0xF8, // MDMCFG0 Modem configuration.
208
209 0x00, // CHANNR Channel number.
210 0x47, // DEVIATN Modem deviation setting (when FSK modulation is enabled).
211 0xB6, // FREND1 Front end RX configuration.
212 0x10, // FREND0 Front end RX configuration.
213 0x18, // MCSM0 Main Radio Control State Machine configuration.
214 0x1D, // FOCCFG Frequency Offset Compensation Configuration.
215 0x1C, // BSCFG Bit synchronization Configuration.
216 0xC7, // AGCCTRL2 AGC control.
217 0x00, // AGCCTRL1 AGC control.
218 0xB2, // AGCCTRL0 AGC control.
219
220 0xEA, // FSCAL3 Frequency synthesizer calibration.
221 0x2A, // FSCAL2 Frequency synthesizer calibration.
222 0x00, // FSCAL1 Frequency synthesizer calibration.
223 0x11, // FSCAL0 Frequency synthesizer calibration.
224 0x59, // FSTEST Frequency synthesizer calibration.
225 0x81, // TEST2 Various test settings.
226 0x35, // TEST1 Various test settings.
227 0x09, // TEST0 Various test settings.
228 0x0B, // IOCFG2 GDO2 output pin configuration.
229 0x06, // IOCFG0D GDO0 output pin configuration. Refer to SmartRF?Studio User Manual for detailed p
-seudo register explanation.
230
231 0x04, // PKTCTRL1 Packet automation control.
232 0x05, // PKTCTRL0 Packet automation control. //地址检测
233 0x00, // ADDR Device address.
234 0x0c // PKTLEN Packet length.
235 };
C51 COMPILER V8.02 CC1100 11/02/2007 10:01:25 PAGE 5
236 */
237 //------------------------------------------------------------------------------------------------------
238 // Chipcon
239 // Product = CC1100
240 // Chip version = E
241 // Crystal accuracy = 40 ppm
242 // X-tal frequency = 26 MHz
243 // RF output power = 0 dBm
244 // RX filterbandwidth = 540.000000 kHz
245 // Deviation = 0.000000
246 // Datarate = 250.000000 kbps
247 // Modulation = (7) MSK
248 // Manchester enable = (0) Manchester disabled
249 // RF Frequency = 433.000000 MHz
250 // Channel spacing = 199.951172 kHz
251 // Channel number = 0
252 // Optimization = Sensitivity
253 // Sync mode = (3) 30/32 sync word bits detected
254 // Format of RX/TX data = (0) Normal mode, use FIFOs for RX and TX
255 // CRC operation = (1) CRC calculation in TX and CRC check in RX enabled
256 // Forward Error Correction = (0) FEC disabled
257 // Length configuration = (1) Variable length packets, packet length configured by the first received byte
- after sync word.
258 // Packetlength = 255
259 // Preamble count = (2) 4 bytes
260 // Append status = 1
261 // Address check = (11) No address check
262 // FIFO autoflush = 0
263 // Device address = 0
264 // GDO0 signal selection = ( 6) Asserts when sync word has been sent / received, and de-asserts at the end
- of the packet
265 // GDO2 signal selection = (11) Serial Clock
266 /*
267 const RF_SETTINGS rfSettings = {
268 0x00,
269
270 0x0B, // FSCTRL1 Frequency synthesizer control.
271 0x00, // FSCTRL0 Frequency synthesizer control.
272 0x10, // FREQ2 Frequency control word, high byte.
273 0xA7, // FREQ1 Frequency control word, middle byte.
274 0x62, // FREQ0 Frequency control word, low byte.
275 //250k
276 0x2D, // MDMCFG4 Modem configuration.
277 0x3B, // MDMCFG3 Modem configuration.
278 0x73, // MDMCFG2 Modem configuration.
279 0x22, // MDMCFG1 Modem configuration.
280 0xF8, // MDMCFG0 Modem configuration.
281
282 // 1.2k
283 0xF5, //MDMCFG4 (x)
284 0x83, //MDMCFG3 (x)
285 0x03, //MDMCFG2 (x)
286 0x22, //MDMCFG1 (x)
287 0xF8, //MDMCFG0 (x)
288
289 0x00, // CHANNR Channel number.
290
291 //0x00, // DEVIATN Modem deviation setting (when FSK modulation is enabled).
292 0x15, //DEVIATN (x)
293 0xB6, // FREND1 Front end RX configuration.
294 0x10, // FREND0 Front end RX configuration.
295 0x18, // MCSM0 Main Radio Control State Machine configuration.
C51 COMPILER V8.02 CC1100 11/02/2007 10:01:25 PAGE 6
296 0x1D, // FOCCFG Frequency Offset Compensation Configuration.
297 0x1C, // BSCFG Bit synchronization Configuration.
298 0xC7, // AGCCTRL2 AGC control.
299 0x00, // AGCCTRL1 AGC control.
300 0xB2, // AGCCTRL0 AGC control.
301
302 0xEA, // FSCAL3 Frequency synthesizer calibration.
303 0x0A, // FSCAL2 Frequency synthesizer calibration.
304 0x00, // FSCAL1 Frequency synthesizer calibration.
305 0x11, // FSCAL0 Frequency synthesizer calibration.
306 0x59, // FSTEST Frequency synthesizer calibration.
307 0x88, // TEST2 Various test settings.
308 0x31, // TEST1 Various test settings.
309 0x0B, // TEST0 Various test settings.
310 0x0B, // IOCFG2 GDO2 output pin configuration.
311 0x06, // IOCFG0D GDO0 output pin configuration. Refer to SmartRF?Studio User Manual for detailed p
-seudo register explanation.
312
313 0x04, // PKTCTRL1 Packet automation control.
314 //0x05, // PKTCTRL1 Packet automation control. //地址检测
315 0x45, // PKTCTRL0 Packet automation control. //可变长数据包,通过同步词汇后的第一个位置配置数据包长⌨️ 快捷键说明
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