edgepf.c

ez-usb fx2编程实例编程实例编程实例

      break;
    }
    case VX_BB:
    {                           
#ifdef REV_CTL    
      SYNCDELAY;                
      INPKTEND = 0x06;          // commit in pkt, new way.. w/skip=0
      SYNCDELAY;                
#else
      SYNCDELAY;                
      INPKTEND = 0x06;          // commit in pkt, old way.. 
      SYNCDELAY;                
#endif      
      *EP0BUF = VX_BB;
      break;
    }
    case VX_BC:
    {                           
#ifdef REV_CTL    
      SYNCDELAY;                
      INPKTEND = 0x86;          // skip in pkt, new way.. w/skip=1
      SYNCDELAY;                
#else
#endif      
      *EP0BUF = VX_BC;
      break;
    }
    case VX_BD:
    {                           
#ifdef REV_CTL    
      SYNCDELAY;                
      EP2BCH = 0x00;
      SYNCDELAY;                
      EP2BCL = 0x20;            // cpu change len out pkt
      SYNCDELAY;                
#else
#endif      
      *EP0BUF = VX_BD;
      break;
    }
    case VX_BE:
    {                           
#ifdef REV_CTL    
      if( ( EP68FIFOFLGS & 0x02 ) /* || zerolenpkt */ )
      { 
        // EP6EF=1, when fifo "empty"...
        *EP0BUF = 0xFF;
      }
      else
      {
        // EP6EF=0 when fifo is "not empty"...
        // ...at this point the pkt. is in the peripheral/cpu domain
      
        SYNCDELAY;                
        ledX_rdvar = LED0_ON;   // debug visual, stuck "ON" to warn developer...
        EP6BCH = 0x00;
        SYNCDELAY;                
        EP6BCL = 0x20;          // cpu change len in pkt
        SYNCDELAY;                
        *EP0BUF = VX_BE;
      
        // ...at this point the pkt. is in the host domain
      }
#else
      if( ( EP68FIFOFLGS & 0x02 ) /* || zerolenpkt */ )
      { 
        // EP6EF=1, when fifo "empty"...
        *EP0BUF = 0xFF;
      }
      else
      {
        // EP6EF=0 when fifo is "not empty"...
        // ...at this point the pkt. is in the peripheral/cpu domain
      
        SYNCDELAY;                
        ledX_rdvar = LED1_ON;   // debug visual, stuck "ON" to warn developer...
        EP6BCH = 0x00;
        SYNCDELAY;                
        EP6BCL = 0x20;          // cpu change len in pkt
        SYNCDELAY;                
        *EP0BUF = VX_BE;
      
        // ...at this point the pkt. is in the host domain
      }
#endif      
      break;
    }
    case VX_BF:
    {                           
#ifdef REV_CTL    
      SYNCDELAY;                
      OUTPKTEND = 0x82;         // skip in pkt, new way.. w/skip=1
      SYNCDELAY;                
#else
#endif      
      *EP0BUF = VX_BF;
      break;
    }
    case VX_C2:
    { // cpu source out data
#ifdef REV_CTL
      if( EP24FIFOFLGS & 0x02 )
      {
        SYNCDELAY;              // 
        FIFORESET = 0x80;       // nak all OUT pkts. from host
        SYNCDELAY;              // 
        FIFORESET = 0x02;       // advance all EP2 buffers to cpu domain
        SYNCDELAY;              // 
        EP2FIFOBUF[0] = 0xAA;   // create newly source pkt. data
        SYNCDELAY;              // 
        EP2BCH = 0x00;
        SYNCDELAY;              // 
        EP2BCL = 0x01;          // commit newly sourced pkt. to interface fifo
      
        // beware of "left over" uncommitted buffers
                                
        SYNCDELAY;              // 
        OUTPKTEND = 0x82;       // skip uncommitted pkt. (second pkt.)
        SYNCDELAY;              // 
        OUTPKTEND = 0x82;       // skip uncommitted pkt. (third pkt.)
        SYNCDELAY;              // 
        OUTPKTEND = 0x82;       // skip uncommitted pkt. (fourth pkt.)
        // note: core will not allow pkts. to get out of sequence
        SYNCDELAY;              // 
        FIFORESET = 0x00;       // release "nak all"
      
        *EP0BUF = VX_C2;
      }
      else
      {
        *EP0BUF = 0xFF;
      }
#else
        *EP0BUF = 0xFF;
#endif
    
      break;
    }
    case VX_C6:
    { 
      REVCTL = 0x03;            // use enh pkt handling and dynamic out
      SYNCDELAY;                // 
      
      *EP0BUF = VX_C6;
      break;
    }
    case VX_C7:
    { 
      SYNCDELAY;                // 
      EP2FIFOCFG = 0x10;        // AUTOOUT=1
      SYNCDELAY;                // 
      EP4FIFOCFG = 0x10;        // AUTOOUT=1
      SYNCDELAY;                // 
      EP6FIFOCFG = 0x10;        // AUTOOUT=1
      SYNCDELAY;                // 
      EP8FIFOCFG = 0x10;        // AUTOOUT=1
      *EP0BUF = VX_C7;
      break;
    }
    case VX_C8:
    { 
      SYNCDELAY;                // 
      EP2FIFOCFG = 0x00;        // AUTOOUT=0
      SYNCDELAY;                // 
      EP4FIFOCFG = 0x00;        // AUTOOUT=0
      SYNCDELAY;                // 
      EP6FIFOCFG = 0x00;        // AUTOOUT=0
      SYNCDELAY;                // 
      EP8FIFOCFG = 0x00;        // AUTOOUT=0
      *EP0BUF = VX_C8;
      break;
    }
    case VX_C9:
    { 
      SYNCDELAY;                // 
      FIFORESET = 0x80;         // activate NAK-ALL to avoid race conditions
      SYNCDELAY;                // 
      FIFORESET = 0x02;         // reset, FIFO 2
      SYNCDELAY;                // 
      FIFORESET = 0x04;         // reset, FIFO 4
      SYNCDELAY;                // 
      FIFORESET = 0x06;         // reset, FIFO 6
      SYNCDELAY;                // 
      FIFORESET = 0x08;         // reset, FIFO 8
      SYNCDELAY;                // 
      FIFORESET = 0x00;         // deactivate NAK-ALL
      
      // NOTE: see TD_Init( ); for proper FIFORESET sequence

      *EP0BUF = VX_C9;
      break;
    }
    case VX_CA:
    { 
      REVCTL = 0x00;            // don't use enh pkt handling and dynamic out
      SYNCDELAY;                // 
      
      *EP0BUF = VX_CA;
      break;
    }
    case VX_D2:
    {                           
#ifdef REV_CTL    
      SYNCDELAY;                
      OUTPKTEND = 0x82;         // skip in pkt, new way.. w/skip=1
      SYNCDELAY;                
#else
      SYNCDELAY;                
      EP2BCL = 0x80;         // skip in pkt, new way.. w/skip=1
      SYNCDELAY;                
#endif      
      *EP0BUF = VX_D2;
      break;
    }
    case VX_D4:
    {                           
#ifdef REV_CTL    
      SYNCDELAY;                
      OUTPKTEND = 0x84;         // skip in pkt, new way.. w/skip=1
      SYNCDELAY;                
#else
      SYNCDELAY;                
      EP4BCL = 0x80;         // skip in pkt, new way.. w/skip=1
      SYNCDELAY;                
#endif      
      *EP0BUF = VX_D4;
      break;
    }
    case VX_D6:
    {                           
#ifdef REV_CTL    
      SYNCDELAY;                
      OUTPKTEND = 0x86;         // skip in pkt, new way.. w/skip=1
      SYNCDELAY;                
#else
      SYNCDELAY;                
      EP6BCL = 0x80;         // skip in pkt, new way.. w/skip=1
      SYNCDELAY;                
#endif      
      *EP0BUF = VX_D2;
      break;
    }
    case VX_D8:
    {                           
#ifdef REV_CTL    
      SYNCDELAY;                
      OUTPKTEND = 0x88;         // skip in pkt, new way.. w/skip=1
      SYNCDELAY;                
#else
      SYNCDELAY;                
      EP8BCL = 0x80;         // skip in pkt, new way.. w/skip=1
      SYNCDELAY;                
#endif      
      *EP0BUF = VX_D8;
      break;
    }
    default:
    {
      ledX_rdvar = LED3_ON;     // debug visual, stuck "ON" to warn developer...
	    return( FALSE );          // no error; command handled OK
    }
	}
  
  EP0BCH = 0;
  EP0BCL = 1;                   // Arm endpoint with # bytes to transfer
  EP0CS |= bmHSNAK;             // Acknowledge handshake phase of device request
  
	return( FALSE );              // no error; command handled OK
}

//-----------------------------------------------------------------------------
// USB Interrupt Handlers
//   The following functions are called by the USB interrupt jump table.
//-----------------------------------------------------------------------------

// Setup Data Available Interrupt Handler
void ISR_Sudav( void ) interrupt 0
{
   GotSUD = TRUE;         // Set flag
   EZUSB_IRQ_CLEAR( );
   USBIRQ = bmSUDAV;      // Clear SUDAV IRQ
}

// Setup Token Interrupt Handler
void ISR_Sutok( void ) interrupt 0
{
   EZUSB_IRQ_CLEAR( );
   USBIRQ = bmSUTOK;      // Clear SUTOK IRQ
}

void ISR_Sof( void ) interrupt 0
{
   EZUSB_IRQ_CLEAR( );
   USBIRQ = bmSOF;        // Clear SOF IRQ
}

void ISR_Ures( void ) interrupt 0
{
   if ( EZUSB_HIGHSPEED( ) )
   {
      pConfigDscr = pHighSpeedConfigDscr;
      pOtherConfigDscr = pFullSpeedConfigDscr;
   }
   else
   {
      pConfigDscr = pFullSpeedConfigDscr;
      pOtherConfigDscr = pHighSpeedConfigDscr;
   }
   
   EZUSB_IRQ_CLEAR( );
   USBIRQ = bmURES;       // Clear URES IRQ
}

void ISR_Susp( void ) interrupt 0
{
   Sleep = TRUE;
   EZUSB_IRQ_CLEAR( );
   USBIRQ = bmSUSP;
}

void ISR_Highspeed( void ) interrupt 0
{
   if ( EZUSB_HIGHSPEED( ) )
   {
      pConfigDscr = pHighSpeedConfigDscr;
      pOtherConfigDscr = pFullSpeedConfigDscr;
   }
   else
   {
      pConfigDscr = pFullSpeedConfigDscr;
      pOtherConfigDscr = pHighSpeedConfigDscr;
   }

   EZUSB_IRQ_CLEAR( );
   USBIRQ = bmHSGRANT;
}
void ISR_Ep0ack( void ) interrupt 0
{
}
void ISR_Stub( void ) interrupt 0
{
}
void ISR_Ep0in( void ) interrupt 0
{
}
void ISR_Ep0out( void ) interrupt 0
{
}
void ISR_Ep1in( void ) interrupt 0
{
}
void ISR_Ep1out( void ) interrupt 0
{
}
void ISR_Ep2inout( void ) interrupt 0
{
}
void ISR_Ep4inout( void ) interrupt 0
{
}
void ISR_Ep6inout( void ) interrupt 0
{
}
void ISR_Ep8inout( void ) interrupt 0
{
}
void ISR_Ibn( void ) interrupt 0
{
}
void ISR_Ep0pingnak( void ) interrupt 0
{
}
void ISR_Ep1pingnak( void ) interrupt 0
{
}
void ISR_Ep2pingnak( void ) interrupt 0
{
}
void ISR_Ep4pingnak( void ) interrupt 0
{
}
void ISR_Ep6pingnak( void ) interrupt 0
{
}
void ISR_Ep8pingnak( void ) interrupt 0
{
}
void ISR_Errorlimit( void ) interrupt 0
{
}
void ISR_Ep2piderror( void ) interrupt 0
{
}
void ISR_Ep4piderror( void ) interrupt 0
{
}
void ISR_Ep6piderror( void ) interrupt 0
{
}
void ISR_Ep8piderror( void ) interrupt 0
{
}
void ISR_Ep2pflag( void ) interrupt 0
{
  ledX_rdvar = LED0_ON;         // visual
  SYNCDELAY;
	EXIF &=  ~0x40;
  SYNCDELAY;
  INT4CLR = 0xFF;               // automatically enabled at POR
  SYNCDELAY;
}
void ISR_Ep4pflag( void ) interrupt 0
{
  ledX_rdvar = LED1_ON;         // visual
  SYNCDELAY;
	EXIF &=  ~0x40;
  SYNCDELAY;
  INT4CLR = 0xFF;               // automatically enabled at POR
  SYNCDELAY;
}
void ISR_Ep6pflag( void ) interrupt 0
{
  ledX_rdvar = LED2_ON;         // visual
  SYNCDELAY;
	EXIF &=  ~0x40;
  SYNCDELAY;
  INT4CLR = 0xFF;               // automatically enabled at POR
  SYNCDELAY;
}
void ISR_Ep8pflag( void ) interrupt 0
{
  ledX_rdvar = LED3_ON;         // visual
  SYNCDELAY;
	EXIF &=  ~0x40;
  SYNCDELAY;
  INT4CLR = 0xFF;               // automatically enabled at POR
  SYNCDELAY;
}
void ISR_Ep2eflag( void ) interrupt 0
{
}
void ISR_Ep4eflag( void ) interrupt 0
{
}
void ISR_Ep6eflag( void ) interrupt 0
{
}
void ISR_Ep8eflag( void ) interrupt 0
{
}
void ISR_Ep2fflag( void ) interrupt 0
{
}
void ISR_Ep4fflag( void ) interrupt 0
{
}
void ISR_Ep6fflag( void ) interrupt 0
{
}
void ISR_Ep8fflag( void ) interrupt 0
{
}
void ISR_GpifComplete( void ) interrupt 0
{
}
void ISR_GpifWaveform( void ) interrupt 0
{
}