📄 t2r1stbc3.mdl
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ProbeSampleTime on
ProbeComplexSignal on
ProbeSignalDimensions off
ProbeFramedSignal off
ProbeWidthDataType "double"
ProbeSampleTimeDataType "double"
ProbeComplexityDataType "double"
ProbeDimensionsDataType "double"
ProbeFrameDataType "double"
}
Block {
BlockType Product
Inputs "2"
Multiplication "Element-wise(.*)"
InputSameDT on
OutDataTypeMode "Same as first input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Zero"
SaturateOnIntegerOverflow on
SampleTime "-1"
}
Block {
BlockType RealImagToComplex
Input "Real and imag"
ConstantPart "0"
SampleTime "-1"
}
Block {
BlockType RelationalOperator
Operator ">="
InputSameDT on
LogicOutDataTypeMode "Logical (see Configuration Parameters: Optimiza"
"tion)"
LogicDataType "uint(8)"
ZeroCross on
SampleTime "-1"
}
Block {
BlockType Selector
InputType "Vector"
IndexMode "One-based"
ElementSrc "Internal"
Elements "1"
RowSrc "Internal"
Rows "1"
ColumnSrc "Internal"
Columns "1"
InputPortWidth "-1"
IndexIsStartValue off
OutputPortSize "1"
}
Block {
BlockType "S-Function"
FunctionName "system"
SFunctionModules "''"
PortCounts "[]"
}
Block {
BlockType SubSystem
ShowPortLabels on
Permissions "ReadWrite"
PermitHierarchicalResolution "All"
SystemSampleTime "-1"
RTWFcnNameOpts "Auto"
RTWFileNameOpts "Auto"
SimViewingDevice off
DataTypeOverride "UseLocalSettings"
MinMaxOverflowLogging "UseLocalSettings"
}
Block {
BlockType Sum
IconShape "rectangular"
Inputs "++"
InputSameDT on
OutDataTypeMode "Same as first input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Floor"
SaturateOnIntegerOverflow on
SampleTime "-1"
}
Block {
BlockType Terminator
}
Block {
BlockType TriggerPort
TriggerType "rising"
StatesWhenEnabling "inherit"
ShowOutputPort off
OutputDataType "auto"
SampleTimeType "triggered"
SampleTime "1"
ZeroCross on
}
}
AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
}
LineDefaults {
FontName "Helvetica"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
System {
Name "T2R1STBC33"
Location [2, 83, 1014, 722]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
ZoomFactor "100"
ReportName "simulink-default.rpt"
Block {
BlockType Reference
Name "AWGN\nChannel1"
Ports [1, 1]
Position [530, 79, 590, 121]
SourceBlock "commchan2/AWGN\nChannel"
SourceType "AWGN Channel"
ShowPortLabels on
seed "67"
noiseMode "Signal to noise ratio (SNR)"
EbNodB "10"
EsNodB "10"
SNRdB "10"
bitsPerSym "1"
Ps "1"
Tsym "1"
variance "1"
}
Block {
BlockType Reference
Name "AWGN\nChannel2"
Ports [1, 1]
Position [530, 209, 590, 251]
SourceBlock "commchan2/AWGN\nChannel"
SourceType "AWGN Channel"
ShowPortLabels on
seed "67"
noiseMode "Signal to noise ratio (SNR)"
EbNodB "10"
EsNodB "10"
SNRdB "10"
bitsPerSym "1"
Ps "1"
Tsym "1"
variance "1"
}
Block {
BlockType Sum
Name "Add"
Ports [2, 1]
Position [645, 133, 680, 197]
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
OutScaling "2^-10"
SaturateOnIntegerOverflow off
}
Block {
BlockType Reference
Name "BPSK\nDemodulator\nBaseband"
Ports [1, 1]
Position [655, 531, 730, 579]
Orientation "left"
SourceBlock "commdigbbndpm2/BPSK\nDemodulator\nBaseband"
SourceType "BPSK Demodulator Baseband"
ShowPortLabels on
Ph "0"
numSamp "1"
}
Block {
BlockType Reference
Name "BPSK\nModulator\nBaseband"
Ports [1, 1]
Position [135, 141, 210, 189]
SourceBlock "commdigbbndpm2/BPSK\nModulator\nBaseband"
SourceType "BPSK Modulator Baseband"
ShowPortLabels on
Ph "0"
numSamp "1"
}
Block {
BlockType Reference
Name "Bernoulli Binary\nGenerator"
Ports [0, 1]
Position [15, 143, 95, 187]
FontName "Arial"
SourceBlock "commrandsrc2/Bernoulli Binary\nGenerator"
SourceType "Bernoulli Binary Generator"
ShowPortLabels on
P "0.5"
seed "61"
Ts "1e-6"
frameBased off
sampPerFrame "1"
orient off
}
Block {
BlockType Reference
Name "Buffer"
Ports [1, 1]
Position [235, 135, 265, 195]
SourceBlock "dspbuff3/Buffer"
SourceType "Buffer"
N "64"
V "0"
ic "0"
}
Block {
BlockType Display
Name "Display"
Ports [1]
Position [80, 509, 175, 581]
Orientation "left"
Decimation "1"
}
Block {
BlockType Display
Name "Display1"
Ports [1]
Position [80, 419, 175, 491]
Orientation "left"
Decimation "1"
}
Block {
BlockType Reference
Name "Error Rate\nCalculation"
Ports [2, 1]
Position [240, 427, 315, 478]
Orientation "left"
SourceBlock "commsink2/Error Rate\nCalculation"
SourceType "Error Rate Calculation"
N "64"
st_delay "0"
cp_mode "Entire frame"
subframe "[]"
PMode "Port"
WsName "ErrorVec"
RsMode2 off
stop off
numErr "100"
maxBits "1e6"
}
Block {
BlockType Reference
Name "Find Delay"
Ports [2, 1]
Position [235, 523, 315, 567]
Orientation "left"
SourceBlock "commutil2/Find Delay"
SourceType "Find Delay"
ShowPortLabels on
corrLength "300"
chgSigOP off
stopUpdate off
numConstDelay "3"
}
Block {
BlockType Reference
Name "Multipath Rayleigh\nFading Channel"
Ports [1, 1]
Position [420, 78, 500, 122]
SourceBlock "commchan2/Multipath Rayleigh\nFading Channel"
SourceType "Multipath Rayleigh Fading Channel"
ShowPortLabels on
Fd "40"
simTs "1e-6"
delayVec "[0]"
gainVecdB "0"
normGain on
Seed "73"
}
Block {
BlockType Reference
Name "Multipath Rayleigh\nFading Channel1"
Ports [1, 1]
Position [420, 208, 500, 252]
SourceBlock "commchan2/Multipath Rayleigh\nFading Channel"
SourceType "Multipath Rayleigh Fading Channel"
ShowPortLabels on
Fd "40"
simTs "1e-6"
delayVec "[0]"
gainVecdB "0"
normGain on
Seed "5430"
}
Block {
BlockType Probe
Name "Probe1"
Ports [1, 1]
Position [310, 24, 465, 56]
ProbeWidth off
ProbeComplexSignal off
}
Block {
BlockType SubSystem
Name "Subsystem"
Ports [1, 2]
Position [310, 133, 380, 197]
TreatAsAtomicUnit off
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
MaskDisplay "disp('Alamouti\\nSTBC')"
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate "none"
MaskIconUnits "autoscale"
System {
Name "Subsystem"
Location [45, 125, 896, 739]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
ZoomFactor "100"
Block {
BlockType Inport
Name "In1"
Position [40, 148, 70, 162]
Port "1"
IconDisplay "Port number"
LatchInput off
Port {
PortNumber 1
Name "x2 x1"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
ShowSigGenPortName on
}
}
Block {
BlockType Gain
Name "Gain"
Position [325, 245, 355, 275]
Gain "-1"
ParameterDataTypeMode "Inherit via internal rule"
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
Port {
PortNumber 1
Name "-x2*"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
ShowSigGenPortName on
}
}
Block {
BlockType Gain
Name "Gain1"
Position [540, 70, 570, 100]
Gain "1/sqrt(2)"
ParameterDataTypeMode "Inherit via internal rule"
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Gain
Name "Gain2"
Position [490, 345, 520, 375]
Gain "1/sqrt(2)"
ParameterDataTypeMode "Inherit via internal rule"
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Math
Name "Math\nFunction"
Ports [1, 1]
Position [265, 245, 295, 275]
Operator "conj"
}
Block {
BlockType Math
Name "Math\nFunction1"
Ports [1, 1]
Position [265, 355, 295, 385]
Operator "conj"
}
Block {
BlockType Reference
Name "Matrix\nConcatenation"
Ports [2, 1]
Position [445, 55, 495, 110]
SourceBlock "simulink/Math\nOperations/Matrix\nConcatena"
"tion"
SourceType "Matrix Concatenation"
numInports "2"
catMethod "Vertical"
Port {
PortNumber 1
Name "x1\n-x2*"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
ShowSigGenPortName on
}
}
Block {
BlockType Reference
Name "Matrix\nConcatenation1"
Ports [2, 1]
Position [400, 330, 450, 385]
SourceBlock "simulink/Math\nOperations/Matrix\nConcatena"
"tion"
SourceType "Matrix Concatenation"
numInports "2"
catMethod "Vertical"
Port {
PortNumber 1
Name "x2\nx1*"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
ShowSigGenPortName on
}
}
Block {
BlockType Probe
Name "Probe"
Ports [1, 1]
Position [590, 274, 745, 306]
ProbeWidth off
ProbeComplexSignal off
}
Block {
BlockType Reference
Name "Submatrix"
Ports [1, 1]
Position [130, 50, 180, 90]
SourceBlock "dspmtrx3/Submatrix"
SourceType "Submatrix"
RowSpan "Range of rows"
RowStartMode "First"
RowStartIndex "1"
RowEndMode "Index"
RowEndIndex "32"
ColSpan "Range of columns"
ColStartMode "First"
ColStartIndex "1"
ColEndMode "Last"
ColEndIndex "1"
Port {
PortNumber 1
Name "x1"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
ShowSigGenPortName on
}
}
Block {
BlockType Reference
Name "Submatrix1"
Ports [1, 1]
Position [125, 240, 175, 280]
SourceBlock "dspmtrx3/Submatrix"
SourceType "Submatrix"
RowSpan "Range of rows"
RowStartMode "Index"
RowStartIndex "33"
RowEndMode "Last"
RowEndIndex "32"
ColSpan "Range of columns"
ColStartMode "First"
ColStartIndex "1"
ColEndMode "Last"
ColEndIndex "1"
Port {
PortNumber 1
Name "x2"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
ShowSigGenPortName on
}
}
Block {
BlockType Terminator
Name "Terminator"
Position [775, 280, 795, 300]
}
Block {
BlockType Outport
Name "Out1"
Position [715, 78, 745, 92]
IconDisplay "Port number"
BusOutputAsStruct off
}
Block {
BlockType Outport
Name "Out2"
Position [720, 353, 750, 367]
Port "2"
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
Name "x2"
Labels [0, 0]
SrcBlock "Submatrix1"
SrcPort 1
Points [50, 0]
Branch {
DstBlock "Math\nFunction"
DstPort 1
}
Branch {
Points [0, 85]
DstBlock "Matrix\nConcatenation1"
DstPort 1
}
}
Line {
SrcBlock "Math\nFunction"
SrcPort 1
DstBlock "Gain"
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