📄 t2r1stbc1.mdl
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RndMeth "Floor"
SaturateOnIntegerOverflow on
}
Block {
BlockType Outport
Port "1"
BusObject "BusObject"
BusOutputAsStruct off
PortDimensions "-1"
SampleTime "-1"
DataType "auto"
OutDataType "sfix(16)"
OutScaling "2^0"
SignalType "auto"
SamplingMode "auto"
OutputWhenDisabled "held"
InitialOutput "[]"
}
Block {
BlockType Probe
ProbeWidth on
ProbeSampleTime on
ProbeComplexSignal on
ProbeSignalDimensions off
ProbeFramedSignal off
ProbeWidthDataType "double"
ProbeSampleTimeDataType "double"
ProbeComplexityDataType "double"
ProbeDimensionsDataType "double"
ProbeFrameDataType "double"
}
Block {
BlockType Product
Inputs "2"
Multiplication "Element-wise(.*)"
InputSameDT on
OutDataTypeMode "Same as first input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Zero"
SaturateOnIntegerOverflow on
SampleTime "-1"
}
Block {
BlockType RealImagToComplex
Input "Real and imag"
ConstantPart "0"
SampleTime "-1"
}
Block {
BlockType RelationalOperator
Operator ">="
InputSameDT on
LogicOutDataTypeMode "Logical (see Configuration Parameters: Optimiza"
"tion)"
LogicDataType "uint(8)"
ZeroCross on
SampleTime "-1"
}
Block {
BlockType Selector
InputType "Vector"
IndexMode "One-based"
ElementSrc "Internal"
Elements "1"
RowSrc "Internal"
Rows "1"
ColumnSrc "Internal"
Columns "1"
InputPortWidth "-1"
IndexIsStartValue off
OutputPortSize "1"
}
Block {
BlockType "S-Function"
FunctionName "system"
SFunctionModules "''"
PortCounts "[]"
}
Block {
BlockType SubSystem
ShowPortLabels on
Permissions "ReadWrite"
PermitHierarchicalResolution "All"
SystemSampleTime "-1"
RTWFcnNameOpts "Auto"
RTWFileNameOpts "Auto"
SimViewingDevice off
DataTypeOverride "UseLocalSettings"
MinMaxOverflowLogging "UseLocalSettings"
}
Block {
BlockType Sum
IconShape "rectangular"
Inputs "++"
InputSameDT on
OutDataTypeMode "Same as first input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Floor"
SaturateOnIntegerOverflow on
SampleTime "-1"
}
Block {
BlockType Terminator
}
Block {
BlockType TriggerPort
TriggerType "rising"
StatesWhenEnabling "inherit"
ShowOutputPort off
OutputDataType "auto"
SampleTimeType "triggered"
SampleTime "1"
ZeroCross on
}
}
AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
}
LineDefaults {
FontName "Helvetica"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
System {
Name "T2R1STBC1"
Location [2, 79, 1022, 718]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
ZoomFactor "100"
ReportName "simulink-default.rpt"
Block {
BlockType Reference
Name "AWGN\nChannel1"
Ports [1, 1]
Position [530, 79, 590, 121]
SourceBlock "commchan2/AWGN\nChannel"
SourceType "AWGN Channel"
ShowPortLabels on
seed "67"
noiseMode "Signal to noise ratio (SNR)"
EbNodB "10"
EsNodB "10"
SNRdB "10"
bitsPerSym "1"
Ps "1"
Tsym "1"
variance "1"
}
Block {
BlockType Reference
Name "AWGN\nChannel2"
Ports [1, 1]
Position [530, 209, 590, 251]
SourceBlock "commchan2/AWGN\nChannel"
SourceType "AWGN Channel"
ShowPortLabels on
seed "67"
noiseMode "Signal to noise ratio (SNR)"
EbNodB "10"
EsNodB "10"
SNRdB "10"
bitsPerSym "1"
Ps "1"
Tsym "1"
variance "1"
}
Block {
BlockType Sum
Name "Add"
Ports [2, 1]
Position [645, 133, 680, 197]
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
OutScaling "2^-10"
SaturateOnIntegerOverflow off
}
Block {
BlockType Reference
Name "BPSK\nDemodulator\nBaseband"
Ports [1, 1]
Position [655, 531, 730, 579]
Orientation "left"
SourceBlock "commdigbbndpm2/BPSK\nDemodulator\nBaseband"
SourceType "BPSK Demodulator Baseband"
ShowPortLabels on
Ph "0"
numSamp "1"
}
Block {
BlockType Reference
Name "BPSK\nModulator\nBaseband"
Ports [1, 1]
Position [135, 141, 210, 189]
SourceBlock "commdigbbndpm2/BPSK\nModulator\nBaseband"
SourceType "BPSK Modulator Baseband"
ShowPortLabels on
Ph "0"
numSamp "1"
}
Block {
BlockType Reference
Name "Bernoulli Binary\nGenerator"
Ports [0, 1]
Position [15, 143, 95, 187]
FontName "Arial"
SourceBlock "commrandsrc2/Bernoulli Binary\nGenerator"
SourceType "Bernoulli Binary Generator"
ShowPortLabels on
P "0.5"
seed "61"
Ts "1e-6"
frameBased off
sampPerFrame "1"
orient off
}
Block {
BlockType Reference
Name "Buffer"
Ports [1, 1]
Position [235, 135, 265, 195]
SourceBlock "dspbuff3/Buffer"
SourceType "Buffer"
N "2"
V "0"
ic "0"
}
Block {
BlockType SubSystem
Name "DSTBC"
Ports [3, 2]
Position [750, 150, 825, 230]
TreatAsAtomicUnit off
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
System {
Name "DSTBC"
Location [144, 97, 996, 704]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
ZoomFactor "100"
Block {
BlockType Inport
Name "In1"
Position [35, 143, 65, 157]
Port "1"
IconDisplay "Port number"
LatchInput off
}
Block {
BlockType Inport
Name "In2"
Position [35, 313, 65, 327]
Port "2"
IconDisplay "Port number"
LatchInput off
Port {
PortNumber 1
Name "h1"
PropagatedSignals "h1"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
ShowSigGenPortName on
}
}
Block {
BlockType Inport
Name "In3"
Position [30, 403, 60, 417]
Port "3"
IconDisplay "Port number"
LatchInput off
Port {
PortNumber 1
Name "h2"
PropagatedSignals "h2"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
ShowSigGenPortName on
}
}
Block {
BlockType Sum
Name "Add"
Ports [2, 1]
Position [625, 133, 660, 197]
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
OutScaling "2^-10"
SaturateOnIntegerOverflow off
Port {
PortNumber 1
Name "x1~"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
ShowSigGenPortName on
}
}
Block {
BlockType Sum
Name "Add1"
Ports [2, 1]
Position [630, 453, 665, 517]
Inputs "+-"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
OutScaling "2^-10"
SaturateOnIntegerOverflow off
Port {
PortNumber 1
Name "x2~"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
ShowSigGenPortName on
}
}
Block {
BlockType Demux
Name "Demux"
Ports [1, 2]
Position [160, 119, 165, 181]
BackgroundColor "black"
ShowName off
Outputs "2"
DisplayOption "bar"
Port {
PortNumber 1
Name "r1"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
ShowSigGenPortName on
}
Port {
PortNumber 2
Name "r2"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
ShowSigGenPortName on
}
}
Block {
BlockType FrameConversion
Name "Frame Conversion"
Position [705, 145, 760, 185]
OutFrame "Frame based"
}
Block {
BlockType FrameConversion
Name "Frame Conversion1"
Position [695, 465, 750, 505]
OutFrame "Frame based"
}
Block {
BlockType FrameConversion
Name "Frame Conversion2"
Position [240, 115, 275, 155]
OutFrame "Frame based"
}
Block {
BlockType FrameConversion
Name "Frame Conversion3"
Position [240, 215, 275, 255]
OutFrame "Frame based"
}
Block {
BlockType Math
Name "Math\nFunction"
Ports [1, 1]
Position [365, 145, 395, 175]
Operator "conj"
}
Block {
BlockType Math
Name "Math\nFunction1"
Ports [1, 1]
Position [325, 220, 355, 250]
Operator "conj"
}
Block {
BlockType Math
Name "Math\nFunction2"
Ports [1, 1]
Position [435, 395, 465, 425]
Operator "conj"
}
Block {
BlockType Probe
Name "Probe"
Ports [1, 3]
Position [365, 34, 520, 66]
ProbeComplexSignal off
ProbeSignalDimensions on
}
Block {
BlockType Probe
Name "Probe1"
Ports [1, 1]
Position [570, 329, 725, 361]
ProbeWidth off
ProbeComplexSignal off
}
Block {
BlockType Probe
Name "Probe2"
Ports [1, 1]
Position [200, 544, 355, 576]
ProbeWidth off
ProbeComplexSignal off
}
Block {
BlockType Product
Name "Product"
Ports [2, 1]
Position [500, 121, 535, 174]
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Product
Name "Product1"
Ports [2, 1]
Position [500, 221, 535, 274]
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Product
Name "Product2"
Ports [2, 1]
Position [500, 371, 535, 424]
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Product
Name "Product3"
Ports [2, 1]
Position [500, 471, 535, 524]
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Terminator
Name "Terminator"
Position [550, 40, 570, 60]
}
Block {
BlockType Terminator
Name "Terminator1"
Position [755, 335, 775, 355]
}
Block {
BlockType Terminator
Name "Terminator2"
Position [385, 550, 405, 570]
}
Block {
BlockType Outport
Name "Out1"
Position [785, 158, 815, 172]
IconDisplay "Port number"
BusOutputAsStruct off
}
Block {
BlockType Outport
Name "Out2"
Position [770, 478, 800, 492]
Port "2"
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
SrcBlock "In1"
SrcPort 1
DstBlock "Demux"
DstPort 1
}
Line {
Name "r1"
Labels [0, 0]
SrcBlock "Demux"
SrcPort 1
DstBlock "Frame Conversion2"
DstPort 1
}
Line {
Name "r2"
Labels [0, 0]
SrcBlock "Demux"
SrcPort 2
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