dif_reg.h

完整的基于Conxant平台的USB电视棒的WIN驱动程序。

//*****************************************************************************
// Reserved                             [31:16]
const DWORD FLD_DIF_SRC_KI                            = 0x0000FF00;
const DWORD FLD_DIF_SRC_KD                            = 0x000000FF;

//*****************************************************************************
const DWORD DIF_BPF_COEFF01         = (DIRECT_IF_REVB_BASE + 0x00000048); // Reg Size 32
//*****************************************************************************
// Reserved                             [31:19]
const DWORD FLD_DIF_BPF_COEFF_0                       = 0x00070000;
// Reserved                             [15:4]
const DWORD FLD_DIF_BPF_COEFF_1                       = 0x0000000F;

//*****************************************************************************
const DWORD DIF_BPF_COEFF23         = (DIRECT_IF_REVB_BASE + 0x0000004c); // Reg Size 32
//*****************************************************************************
// Reserved                             [31:22]
const DWORD FLD_DIF_BPF_COEFF_2                       = 0x003F0000;
// Reserved                             [15:7]
const DWORD FLD_DIF_BPF_COEFF_3                       = 0x0000007F;

//*****************************************************************************
const DWORD DIF_BPF_COEFF45         = (DIRECT_IF_REVB_BASE + 0x00000050); // Reg Size 32
//*****************************************************************************
// Reserved                             [31:24]
const DWORD FLD_DIF_BPF_COEFF_4                       = 0x00FF0000;
// Reserved                             [15:8]
const DWORD FLD_DIF_BPF_COEFF_5                       = 0x000000FF;

//*****************************************************************************
const DWORD DIF_BPF_COEFF67         = (DIRECT_IF_REVB_BASE + 0x00000054); // Reg Size 32
//*****************************************************************************
// Reserved                             [31:25]
const DWORD FLD_DIF_BPF_COEFF_6                       = 0x01FF0000;
// Reserved                             [15:9]
const DWORD FLD_DIF_BPF_COEFF_7                       = 0x000001FF;

//*****************************************************************************
const DWORD DIF_BPF_COEFF89         = (DIRECT_IF_REVB_BASE + 0x00000058); // Reg Size 32
//*****************************************************************************
// Reserved                             [31:26]
const DWORD FLD_DIF_BPF_COEFF_8                       = 0x03FF0000;
// Reserved                             [15:10]
const DWORD FLD_DIF_BPF_COEFF_9                       = 0x000003FF;

//*****************************************************************************
const DWORD DIF_BPF_COEFF1011       = (DIRECT_IF_REVB_BASE + 0x0000005C); // Reg Size 32
//*****************************************************************************
// Reserved                             [31:27]
const DWORD FLD_DIF_BPF_COEFF_10                      = 0x07FF0000;
// Reserved                             [15:11]
const DWORD FLD_DIF_BPF_COEFF_11                      = 0x000007FF;

//*****************************************************************************
const DWORD DIF_BPF_COEFF1213       = (DIRECT_IF_REVB_BASE + 0x00000060); // Reg Size 32
//*****************************************************************************
// Reserved                             [31:27]
const DWORD FLD_DIF_BPF_COEFF_12                      = 0x07FF0000;
// Reserved                             [15:12]
const DWORD FLD_DIF_BPF_COEFF_13                      = 0x00000FFF;

//*****************************************************************************
const DWORD DIF_BPF_COEFF1415       = (DIRECT_IF_REVB_BASE + 0x00000064); // Reg Size 32
//*****************************************************************************
// Reserved                             [31:28]
const DWORD FLD_DIF_BPF_COEFF_14                      = 0x0FFF0000;
// Reserved                             [15:12]
const DWORD FLD_DIF_BPF_COEFF_15                      = 0x00000FFF;

//*****************************************************************************
const DWORD DIF_BPF_COEFF1617       = (DIRECT_IF_REVB_BASE + 0x00000068); // Reg Size 32
//*****************************************************************************
// Reserved                             [31:29]
const DWORD FLD_DIF_BPF_COEFF_16                      = 0x1FFF0000;
// Reserved                             [15:13]
const DWORD FLD_DIF_BPF_COEFF_17                      = 0x00001FFF;

//*****************************************************************************
const DWORD DIF_BPF_COEFF1819       = (DIRECT_IF_REVB_BASE + 0x0000006C); // Reg Size 32
//*****************************************************************************
// Reserved                             [31:29]
const DWORD FLD_DIF_BPF_COEFF_18                      = 0x1FFF0000;
// Reserved                             [15:13]
const DWORD FLD_DIF_BPF_COEFF_19                      = 0x00001FFF;

//*****************************************************************************
const DWORD DIF_BPF_COEFF2021       = (DIRECT_IF_REVB_BASE + 0x00000070); // Reg Size 32
//*****************************************************************************
// Reserved                             [31:29]
const DWORD FLD_DIF_BPF_COEFF_20                      = 0x1FFF0000;
// Reserved                             [15:14]
const DWORD FLD_DIF_BPF_COEFF_21                      = 0x00003FFF;

//*****************************************************************************
const DWORD DIF_BPF_COEFF2223       = (DIRECT_IF_REVB_BASE + 0x00000074); // Reg Size 32
//*****************************************************************************
// Reserved                             [31:30]
const DWORD FLD_DIF_BPF_COEFF_22                      = 0x3FFF0000;
// Reserved                             [15:14]
const DWORD FLD_DIF_BPF_COEFF_23                      = 0x00003FFF;

//*****************************************************************************
const DWORD DIF_BPF_COEFF2425       = (DIRECT_IF_REVB_BASE + 0x00000078); // Reg Size 32
//*****************************************************************************
// Reserved                             [31:30]
const DWORD FLD_DIF_BPF_COEFF_24                      = 0x3FFF0000;
// Reserved                             [15:14]
const DWORD FLD_DIF_BPF_COEFF_25                      = 0x00003FFF;

//*****************************************************************************
const DWORD DIF_BPF_COEFF2627       = (DIRECT_IF_REVB_BASE + 0x0000007C); // Reg Size 32
//*****************************************************************************
// Reserved                             [31:30]
const DWORD FLD_DIF_BPF_COEFF_26                      = 0x3FFF0000;
// Reserved                             [15:14]
const DWORD FLD_DIF_BPF_COEFF_27                      = 0x00003FFF;

//*****************************************************************************
const DWORD DIF_BPF_COEFF2829       = (DIRECT_IF_REVB_BASE + 0x00000080); // Reg Size 32
//*****************************************************************************
// Reserved                             [31:30]
const DWORD FLD_DIF_BPF_COEFF_28                      = 0x3FFF0000;
// Reserved                             [15:14]
const DWORD FLD_DIF_BPF_COEFF_29                      = 0x00003FFF;

//*****************************************************************************
const DWORD DIF_BPF_COEFF3031       = (DIRECT_IF_REVB_BASE + 0x00000084); // Reg Size 32
//*****************************************************************************
// Reserved                             [31:30]
const DWORD FLD_DIF_BPF_COEFF_30                      = 0x3FFF0000;
// Reserved                             [15:14]
const DWORD FLD_DIF_BPF_COEFF_31                      = 0x00003FFF;

//*****************************************************************************
const DWORD DIF_BPF_COEFF3233       = (DIRECT_IF_REVB_BASE + 0x00000088); // Reg Size 32
//*****************************************************************************
// Reserved                             [31:30]
const DWORD FLD_DIF_BPF_COEFF_32                      = 0x3FFF0000;
// Reserved                             [15:14]
const DWORD FLD_DIF_BPF_COEFF_33                      = 0x00003FFF;

//*****************************************************************************
const DWORD DIF_BPF_COEFF3435       = (DIRECT_IF_REVB_BASE + 0x0000008C); // Reg Size 32
//*****************************************************************************
// Reserved                             [31:30]
const DWORD FLD_DIF_BPF_COEFF_34                      = 0x3FFF0000;
// Reserved                             [15:14]
const DWORD FLD_DIF_BPF_COEFF_35                      = 0x00003FFF;

//*****************************************************************************
const DWORD DIF_BPF_COEFF36         = (DIRECT_IF_REVB_BASE + 0x00000090); // Reg Size 32
//*****************************************************************************
// Reserved                             [31:30]
const DWORD FLD_DIF_BPF_COEFF_36                      = 0x3FFF0000;
// Reserved                             [15:0]

//*****************************************************************************
const DWORD DIF_RPT_VARIANCE        = (DIRECT_IF_REVB_BASE + 0x00000094); // Reg Size 32
//*****************************************************************************
// Reserved                             [31:20]
const DWORD FLD_DIF_RPT_VARIANCE                      = 0x000FFFFF;

//*****************************************************************************
const DWORD DIF_SOFT_RST_CTRL_REVB      = (DIRECT_IF_REVB_BASE + 0x00000098); // Reg Size 32
//*****************************************************************************
// Reserved                             [31:8]
const DWORD FLD_DIF_DIF_SOFT_RST                      = 0x00000080;
const DWORD FLD_DIF_DIF_REG_RST_MSK                   = 0x00000040;
const DWORD FLD_DIF_AGC_RST_MSK                       = 0x00000020;
const DWORD FLD_DIF_CMP_RST_MSK                       = 0x00000010;
const DWORD FLD_DIF_AVS_RST_MSK                       = 0x00000008;
const DWORD FLD_DIF_NYQ_RST_MSK                       = 0x00000004;
const DWORD FLD_DIF_DIF_SRC_RST_MSK                   = 0x00000002;
const DWORD FLD_DIF_PLL_RST_MSK                       = 0x00000001;

//*****************************************************************************
const DWORD DIF_PLL_FREQ_ERR        = (DIRECT_IF_REVB_BASE + 0x0000009C); // Reg Size 32
//*****************************************************************************
// Reserved                             [31:25]
const DWORD FLD_DIF_CTL_IP                            = 0x01FFFFFF;

#endif