dif_reg.h

完整的基于Conxant平台的USB电视棒的WIN驱动程序。

/*+++ *******************************************************************\
*
*  DIF_reg.h
*
*  Copyright and Disclaimer:
*
*     ---------------------------------------------------------------
*     This software is provided "AS IS" without warranty of any kind,
*     either expressed or implied, including but not limited to the
*     implied warranties of noninfringement, merchantability and/or
*     fitness for a particular purpose.
*     ---------------------------------------------------------------
*
*     Copyright (c) 2008 Conexant Systems, Inc.
*     All rights reserved.
*
*  Register definitions for the DIF portion of Polaris
*
\******************************************************************* ---*/

#ifndef __DIF_REG__
#define __DIF_REG__
//*****************************************************************************
// Corona Rev B DirectIF registers
//*****************************************************************************

//*****************************************************************************
const DWORD DIRECT_IF_REVB_BASE = 0x00300;

//*****************************************************************************
const DWORD DIF_PLL_FREQ_WORD       = (DIRECT_IF_REVB_BASE + 0x00000000); // Reg Size 32
//*****************************************************************************
const DWORD FLD_DIF_PLL_LOCK                          = 0x80000000;
// Reserved                                [30:29]
const DWORD FLD_DIF_PLL_FREE_RUN                      = 0x10000000;
const DWORD FLD_DIF_PLL_FREQ                          = 0x0FFFFFFF;

//*****************************************************************************
const DWORD DIF_PLL_CTRL            = (DIRECT_IF_REVB_BASE + 0x00000004); // Reg Size 32
//*****************************************************************************
const DWORD FLD_DIF_KD_PD                             = 0xFF000000;
// Reserved                             [23:20]
const DWORD FLD_DIF_KDS_PD                            = 0x000F0000;
const DWORD FLD_DIF_KI_PD                             = 0x0000FF00;
// Reserved                             [7:4]
const DWORD FLD_DIF_KIS_PD                            = 0x0000000F;

//*****************************************************************************
const DWORD DIF_PLL_CTRL1           = (DIRECT_IF_REVB_BASE + 0x00000008); // Reg Size 32
//*****************************************************************************
const DWORD FLD_DIF_KD_FD                             = 0xFF000000;
// Reserved                             [23:20]
const DWORD FLD_DIF_KDS_FD                            = 0x000F0000;
const DWORD FLD_DIF_KI_FD                             = 0x0000FF00;
const DWORD FLD_DIF_SIG_PROP_SZ                       = 0x000000F0;
const DWORD FLD_DIF_KIS_FD                            = 0x0000000F;

//*****************************************************************************
const DWORD DIF_PLL_CTRL2           = (DIRECT_IF_REVB_BASE + 0x0000000C); // Reg Size 32
//*****************************************************************************
const DWORD FLD_DIF_PLL_AGC_REF                       = 0xFFF00000;
const DWORD FLD_DIF_PLL_AGC_KI                        = 0x000F0000;
// Reserved                             [15]
const DWORD FLD_DIF_FREQ_LIMIT                        = 0x00007000;
const DWORD FLD_DIF_K_FD                              = 0x00000F00;
const DWORD FLD_DIF_DOWNSMPL_FD                       = 0x000000FF;

//*****************************************************************************
const DWORD DIF_PLL_CTRL3           = (DIRECT_IF_REVB_BASE + 0x00000010); // Reg Size 32
//*****************************************************************************
// Reserved                             [31:16]
const DWORD FLD_DIF_PLL_AGC_EN                        = 0x00008000;
// Reserved                             [14:12]
const DWORD FLD_DIF_PLL_MAN_GAIN                      = 0x00000FFF;

//*****************************************************************************
const DWORD DIF_AGC_IF_REF          = (DIRECT_IF_REVB_BASE + 0x00000014); // Reg Size 32
//*****************************************************************************
const DWORD FLD_DIF_K_AGC_RF                          = 0xF0000000;
const DWORD FLD_DIF_K_AGC_IF                          = 0x0F000000;
const DWORD FLD_DIF_K_AGC_INT                         = 0x00F00000;
// Reserved                             [19:12]
const DWORD FLD_DIF_IF_REF                            = 0x00000FFF;

//*****************************************************************************
const DWORD DIF_AGC_CTRL_IF         = (DIRECT_IF_REVB_BASE + 0x00000018); // Reg Size 32
//*****************************************************************************
const DWORD FLD_DIF_IF_MAX                            = 0xFF000000;
const DWORD FLD_DIF_IF_MIN                            = 0x00FF0000;
const DWORD FLD_DIF_IF_AGC                            = 0x0000FFFF;

//*****************************************************************************
const DWORD DIF_AGC_CTRL_INT        = (DIRECT_IF_REVB_BASE + 0x0000001C); // Reg Size 32
//*****************************************************************************
const DWORD FLD_DIF_INT_MAX                           = 0xFF000000;
const DWORD FLD_DIF_INT_MIN                           = 0x00FF0000;
const DWORD FLD_DIF_INT_AGC                           = 0x0000FFFF;

//*****************************************************************************
const DWORD DIF_AGC_CTRL_RF         = (DIRECT_IF_REVB_BASE + 0x00000020); // Reg Size 32
//*****************************************************************************
const DWORD FLD_DIF_RF_MAX                            = 0xFF000000;
const DWORD FLD_DIF_RF_MIN                            = 0x00FF0000;
const DWORD FLD_DIF_RF_AGC                            = 0x0000FFFF;

//*****************************************************************************
const DWORD DIF_AGC_IF_INT_CURRENT  = (DIRECT_IF_REVB_BASE + 0x00000024); // Reg Size 32
//*****************************************************************************
const DWORD FLD_DIF_IF_AGC_IN                         = 0xFFFF0000;
const DWORD FLD_DIF_INT_AGC_IN                        = 0x0000FFFF;

//*****************************************************************************
const DWORD DIF_AGC_RF_CURRENT      = (DIRECT_IF_REVB_BASE + 0x00000028); // Reg Size 32
//*****************************************************************************
// Reserved                            [31:16]
const DWORD FLD_DIF_RF_AGC_IN                         = 0x0000FFFF;

//*****************************************************************************
const DWORD DIF_VIDEO_AGC_CTRL      = (DIRECT_IF_REVB_BASE + 0x0000002C); // Reg Size 32
//*****************************************************************************
const DWORD FLD_DIF_AFD                               = 0xC0000000;
const DWORD FLD_DIF_K_VID_AGC                         = 0x30000000;
const DWORD FLD_DIF_LINE_LENGTH                       = 0x0FFF0000;
const DWORD FLD_DIF_AGC_GAIN                          = 0x0000FFFF;

//*****************************************************************************
const DWORD DIF_VID_AUD_OVERRIDE    = (DIRECT_IF_REVB_BASE + 0x00000030); // Reg Size 32
//*****************************************************************************
const DWORD FLD_DIF_AUDIO_AGC_OVERRIDE                = 0x80000000;
// Reserved                             [30:30]
const DWORD FLD_DIF_AUDIO_MAN_GAIN                    = 0x3F000000;
// Reserved                             [23:17]
const DWORD FLD_DIF_VID_AGC_OVERRIDE                  = 0x00010000;
const DWORD FLD_DIF_VID_MAN_GAIN                      = 0x0000FFFF;

//*****************************************************************************
const DWORD DIF_AV_SEP_CTRL         = (DIRECT_IF_REVB_BASE + 0x00000034); // Reg Size 32
//*****************************************************************************
const DWORD FLD_DIF_LPF_FREQ                          = 0xC0000000;
const DWORD FLD_DIF_AV_PHASE_INC                      = 0x3F000000;
const DWORD FLD_DIF_AUDIO_FREQ                        = 0x00FFFFFF;

//*****************************************************************************
const DWORD DIF_COMP_FLT_CTRL       = (DIRECT_IF_REVB_BASE + 0x00000038); // Reg Size 32
//*****************************************************************************
// Reserved                            [31:24]
const DWORD FLD_DIF_IIR23_R2                          = 0x00FF0000;
const DWORD FLD_DIF_IIR23_R1                          = 0x0000FF00;
const DWORD FLD_DIF_IIR1_R1                           = 0x000000FF;

//*****************************************************************************
const DWORD DIF_MISC_CTRL           = (DIRECT_IF_REVB_BASE + 0x0000003C); // Reg Size 32
//*****************************************************************************
const DWORD FLD_DIF_DIF_BYPASS                        = 0x80000000;
const DWORD FLD_DIF_FM_NYQ_GAIN                       = 0x40000000;
const DWORD FLD_DIF_RF_AGC_ENA                        = 0x20000000;
const DWORD FLD_DIF_INT_AGC_ENA                       = 0x10000000;
const DWORD FLD_DIF_IF_AGC_ENA                        = 0x08000000;
const DWORD FLD_DIF_FORCE_RF_IF_LOCK                  = 0x04000000;
const DWORD FLD_DIF_VIDEO_AGC_ENA                     = 0x02000000;
const DWORD FLD_DIF_RF_AGC_INV                        = 0x01000000;
const DWORD FLD_DIF_INT_AGC_INV                       = 0x00800000;
const DWORD FLD_DIF_IF_AGC_INV                        = 0x00400000;
const DWORD FLD_DIF_SPEC_INV                          = 0x00200000;
const DWORD FLD_DIF_AUD_FULL_BW                       = 0x00100000;
const DWORD FLD_DIF_AUD_SRC_SEL                       = 0x00080000;
// Reserved                             [18]
const DWORD FLD_DIF_IF_FREQ                           = 0x00030000;
// Reserved                             [15:14]
const DWORD FLD_DIF_TIP_OFFSET                        = 0x00003F00;
// Reserved                             [7:5]
const DWORD FLD_DIF_DITHER_ENA                        = 0x00000010;
// Reserved                             [3:1]
const DWORD FLD_DIF_RF_IF_LOCK                        = 0x00000001;

//*****************************************************************************
const DWORD DIF_SRC_PHASE_INC       = (DIRECT_IF_REVB_BASE + 0x00000040); // Reg Size 32
//*****************************************************************************
// Reserved                             [31:29]
const DWORD FLD_DIF_PHASE_INC                         = 0x1FFFFFFF;

//*****************************************************************************
const DWORD DIF_SRC_GAIN_CONTROL    = (DIRECT_IF_REVB_BASE + 0x00000044); // Reg Size 32