thresher.cpp

完整的基于Conxant平台的USB电视棒的WIN驱动程序。

DWORD Thresher::getCopyProtectStatus()
{
    DWORD decoder_status = 0;
    DWORD mv_status      = 0;
    DWORD ret_status     = 0;

    if (!_powered_up)
    {
        mv_status = CX_PROTECTION_DISABLED;
    }
    else
    {
        _p_registers->readDword(GEN_STAT, &decoder_status);

        //if not powered up or if video is not present
        if ((decoder_status & 0x00200000) == 0)
        {
            mv_status = CX_PROTECTION_DISABLED;
        }
        else
        {
            mv_status = decoder_status & COPY_PROTECTION_MASK;
            mv_status = mv_status >> 4;
        }
    }

    switch (mv_status)
    {
    case CX_PROTECTION_DISABLED:
        ret_status = COPY_PROTECTION_NOT_DETECTED;
        break;

    case CX_PROTECTION_PSP:
        ret_status = COPY_PROTECTION_CS_TYPE1_DETECTED;
        break;

    case CX_PROTECTION_TYPE2CS:
    case CX_PROTECTION_PSP_TYPE2CS:
        ret_status = COPY_PROTECTION_CS_TYPE2_DETECTED;
        break;

    case CX_PROTECTION_TYPE3CS:
    case CX_PROTECTION_PSP_TYPE3CS:
        ret_status = COPY_PROTECTION_CS_TYPE3_DETECTED;
        break;
    }

    return ret_status;
}

/////////////////////////////////////////////////////////////////////////////////////////
VOID Thresher::videoMute()
{
    _video_muted = true;
    _p_registers->lock();
    _p_registers->writeByte(BRIGHTNESS_CTRL_BYTE, 0);
    _p_registers->writeByte(USAT_CTRL_BYTE, 0);
    _p_registers->writeByte(VSAT_CTRL_BYTE, 0);
    _p_registers->writeByte(CONTRAST_CTRL_BYTE, 0);
    _p_registers->unlock();
}

/////////////////////////////////////////////////////////////////////////////////////////
VOID Thresher::videoUnmute()
{
    _video_muted = false;
    _p_registers->lock();
    _p_registers->writeByte(BRIGHTNESS_CTRL_BYTE, _preserved_brightness);
    _p_registers->writeByte(USAT_CTRL_BYTE, _preserved_saturation);
    _p_registers->writeByte(VSAT_CTRL_BYTE, _preserved_saturation);
    _p_registers->writeByte(CONTRAST_CTRL_BYTE, _preserved_contrast);
    _p_registers->unlock();
}

/////////////////////////////////////////////////////////////////////////////////////////
VOID Thresher::videoSetGrey(BOOLEAN enableGrey)
{
    // If Video was already muted - say due to Copy Protection,
    // we will bail out
    if (_video_muted) 
        return;

    if (enableGrey)
    {
        _p_registers->lock();
        _p_registers->writeByte(BRIGHTNESS_CTRL_BYTE, 0x5A);
        _p_registers->writeByte(USAT_CTRL_BYTE, 0);
        _p_registers->writeByte(VSAT_CTRL_BYTE, 0);
        _p_registers->writeByte(CONTRAST_CTRL_BYTE, 0);
        _p_registers->unlock();
    }
    else
    {
        videoUnmute();
    }
}

/////////////////////////////////////////////////////////////////////////////////////////
VOID Thresher::powerDown()
{
    // [todo] finish this, same as corona
    _powered_up = false;
}

/////////////////////////////////////////////////////////////////////////////////////////
VOID Thresher::powerUp()
{
    _powered_up = true;

    setVideoMode(_video_mode);
    setResolution(_width, _height);
    setVideoInput(_video_input, _input_mux);

    setBrightness(_brightness);
    setContrast(_contrast);
    setHue(_hue);
    setSharpness(_sharpness);
    setSaturation(_saturation);    

    // Initialize some registers
    initializeThresher();
}

DWORD Thresher::initializeThresher()
{    
    // set Range to 1
    _p_registers->readModifyWriteDword(LUMA_CTRL, FLD_RANGE,  _p_registers->Set_Field(FLD_RANGE, 0x1) );
    //set core sel to 1
    _p_registers->readModifyWriteDword(CHROMA_CTRL, FLD_C_CORE_SEL,  _p_registers->Set_Field(FLD_C_CORE_SEL, 0x1) );

    _p_registers->readModifyWriteDword(SRC_COMB_CFG, FLD_UV_LPF_SEL,  _p_registers->Set_Field(FLD_UV_LPF_SEL, 0x2) );
    _p_registers->readModifyWriteDword(SRC_COMB_CFG, FLD_LUMA_LPF_SEL,  _p_registers->Set_Field(FLD_LUMA_LPF_SEL, 0x0) );

    return(0); // No Error
}

/////////////////////////////////////////////////////////////////////////////////////////
//Thresher::setInputMux
//
// There are eight possible inputs to Mako, and three input channels.
// Channel 1 is the primary video channel.
// Channels 2 and 3 can take either tuner audio or the S-video chroma signal.
//
// Channel 1 can be set to any input.
// Channel 2 can be set to inputs 4-6
// Channel 3 can be set to inputs 7-8
//
// Bit 17 of CHIP_CTRL selects rather we use channel 2 or channel 3 for the secondary input
// Bit 18 of CHIP_CTRL selects whether we use ADC2 in single or dual mode (for component input)
//
// input_mux is a DWORD containing up to three bytes representing the input mux to use for
// the three video input channels for the currently select input mode
//
// input_channel is DWORD that has a one-to-one correspondence with input_mux that indicates which of the
// three input channels that input mux should be mapped to.
//
// the high byte of input_channel, if nono zero, indicates that the device should be put in dual ADC2 mode
// for use with component video.
//
// This function requires that there be no overlap in input mux and channel for the specified input
// requested, i.e., each input channel must occur only once in the input_channel bytes
//

VOID Thresher::setInputMux(DWORD input_mux)
{
    _p_colibri->setInputMux(input_mux);
}

/////////////////////////////////////////////////////////////////////////////////////////
VOID Thresher::setVideoInput(DWORD video_input, DWORD input_mux)
{
    _p_registers->lock();

    DWORD value = 0;
    _video_input = video_input;

    _input_mux = input_mux;

    setInputMux(input_mux);

    //Set the mode control based on the input type.  This is different
    // for S-Video than for composite or tuner
    switch(video_input)
    {

    case VIDEO_INPUT_COMPOSITE:
    case VIDEO_INPUT_COMPOSITE_YC:
        // MAE 12 Sep 2006 FOOFOO
        // If _p_DIF is non-null, then this is a board using the DIF for the tuner
        // Disable the use of  DIF
        if (_p_DIF)
        {
            //following can_hu's suggestion
            _p_registers->readDword(AFE_CTRL, &value);
            value |= (0<<13)|(1<<4);
            value  &= ~(1<<5);

            // Ben 10,23 added
            value &= (~(0x1FF8000));//set [24:23] [22:15] to 0
            value |= 0x1000000;// set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0
            _p_registers->writeDword(AFE_CTRL, value);   

            _p_registers->readDword(OUT_CTRL1, &value);
            value |= (1<<7);            
            _p_registers->writeDword(OUT_CTRL1, value); 
            // Set vip 1.1 output mode
            _p_registers->readModifyWriteDword(OUT_CTRL1, FLD_OUT_MODE, OUT_MODE_VIP11);

            _p_DIF->setStandard(DIF_USE_BASEBAND);  // Tell DIF object to go to baseband mode

            // Read the DFE_CTRL1 register
            _p_registers->readDword(DFE_CTRL1, &value);

            // enable the VBI_GATE_EN
            value |= FLD_VBI_GATE_EN;

            // Enable the auto-VGA enable
            value |= FLD_VGA_AUTO_EN;

            // Write it back
            _p_registers->writeDword(DFE_CTRL1, value);

        }

        // Disable auto config of registers
        _p_registers->readModifyWriteDword(MODE_CTRL, FLD_ACFG_DIS, _p_registers->Set_Field(FLD_ACFG_DIS, 1));

        // Set CVBS input mode
        _p_registers->readModifyWriteDword(MODE_CTRL, FLD_INPUT_MODE, _p_registers->Set_Field(FLD_INPUT_MODE, INPUT_MODE_CVBS_0));

        break;

    case VIDEO_INPUT_SVIDEO:
        {
        // MAE 12 Sep 2006 FOOFOO
        // If _p_DIF is non-null, then this is a board using the DIF for the tuner
        // Disable the use of  DIF
        if (_p_DIF)
        {   
            _p_registers->readDword(AFE_CTRL, &value);
            // Ben 10,23 added
            value &= (~(0x1FF8000));//set [24:23] [22:15] to 0
            value |= 0x1000000;// set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0
            _p_registers->writeDword(AFE_CTRL, value);

            _p_DIF->setStandard(DIF_USE_BASEBAND);  // Tell DIF object to go to baseband mode

            // Read the DFE_CTRL1 register
            _p_registers->readDword(DFE_CTRL1, &value);

            // enable the VBI_GATE_EN
            value |= FLD_VBI_GATE_EN;

            // Enable the auto-VGA enable
            value |= FLD_VGA_AUTO_EN;

            // Write it back
            _p_registers->writeDword(DFE_CTRL1, value);

       }

        // Disable auto config of registers
        _p_registers->readModifyWriteDword(MODE_CTRL, FLD_ACFG_DIS, _p_registers->Set_Field(FLD_ACFG_DIS, 1));

        // Set YC input mode
        _p_registers->readModifyWriteDword(MODE_CTRL, FLD_INPUT_MODE, _p_registers->Set_Field(FLD_INPUT_MODE, INPUT_MODE_YC_1));

        // Chroma to ADC2
        _p_registers->readDword(AFE_CTRL, &value);
        value |= FLD_CHROMA_IN_SEL; //set the chroma in select

        // Clear VGA_SEL_CH2 and VGA_SEL_CH3 (bits 7 and 8)  This sets them to use video
        // rather than audio.  Only one of the two will be in use.
        value &= ~(FLD_VGA_SEL_CH2 | FLD_VGA_SEL_CH3);        

        _p_registers->writeDword(AFE_CTRL, value);
          
        _p_colibri->SetMode(Colibri::AFE_MODE_BASEBAND);
        }

        break;

    case VIDEO_INPUT_COMPONENT:

        // MAE 12 Sep 2006 FOOFOO
        // If _p_DIF is non-null, then this is a board using the DIF for the tuner
        // Disable the use of  DIF
        if (_p_DIF)
        {
            // set IF_MODE to 0x0 for baseband (using Nemo)
            _p_registers->readDword(AFE_CTRL, &value);
            value |= (1<<23)|(1<<24);    //select base band mode Y/U/V
            _p_registers->writeDword(AFE_CTRL, value);

            _p_DIF->setStandard(DIF_USE_BASEBAND);  // Tell DIF object to go to baseband mode

            // Read the DFE_CTRL1 register
            _p_registers->readDword(DFE_CTRL1, &value);

            // enable the VBI_GATE_EN
            value |= FLD_VBI_GATE_EN;

            // Enable the auto-VGA enable
            value |= FLD_VGA_AUTO_EN;

            // Write it back
            _p_registers->writeDword(DFE_CTRL1, value);
         }
 
        // Disable auto config of registers
        _p_registers->readModifyWriteDword(MODE_CTRL, FLD_ACFG_DIS, _p_registers->Set_Field(FLD_ACFG_DIS, 1));

        // Set component input mode
        _p_registers->readModifyWriteDword(MODE_CTRL, FLD_INPUT_MODE, _p_registers->Set_Field(FLD_INPUT_MODE, INPUT_MODE_YUV_3));


       break;

    case VIDEO_INPUT_TUNER:
    default:
        // MAE 12 Sep 2006 FOOFOO
        // If _p_DIF is non-null, then this is a board using the DIF for the tuner
        // Enable the DIF for the tuner
        if (_p_DIF)
        {
            // Reinitialize the DIF
            _p_DIF->setStandard(_video_standard);

            // Make sure bypass is cleared
            _p_registers->readDword(DIF_MISC_CTRL, &value);

            // Clear the bypass bit
            value &= ~FLD_DIF_DIF_BYPASS;

            // Enable the use of the DIF block
            _p_registers->writeDword(DIF_MISC_CTRL, value);            

            // Read the DFE_CTRL1 register
            _p_registers->readDword(DFE_CTRL1, &value);

            // Disable the VBI_GATE_EN
            value &= ~FLD_VBI_GATE_EN;

            // Enable the auto-VGA enable, AGC, and set the skip count to 2
            value |= FLD_VGA_AUTO_EN | FLD_AGC_AUTO_EN | 0x00200000;

            // Write it back
            _p_registers->writeDword(DFE_CTRL1, value);

            // Wait 15 ms
            pauseThread(15);

            // Disable the auto-VGA enable AGC
            value &= ~(FLD_VGA_AUTO_EN);

            // Write it back
            _p_registers->writeDword(DFE_CTRL1, value);

            //Enable Polaris B0 AGC output
            if(_p_device)
            {
                USHORT rev_id=_p_device->getRevID();
                if(rev_id>=POLARIS_REVID_A0)
                {
                    _p_registers->readDword(PIN_CTRL, &value);
                    value |=(FLD_OEF_AGC_RF)|(FLD_OEF_AGC_IFVGA)|(FLD_OEF_AGC_IF);
                    _p_registers->writeDword(PIN_CTRL, value);
                }
            }
        }

        // Set vip 1.1 output mode
        _p_registers->readModifyWriteDword(OUT_CTRL1, FLD_OUT_MODE, OUT_MODE_VIP11);
        
        // Disable auto config of registers
        _p_registers->readModifyWriteDword(MODE_CTRL, FLD_ACFG_DIS, _p_registers->Set_Field(FLD_ACFG_DIS, 1));

        // Set CVBS input mode
        _p_registers->readModifyWriteDword(MODE_CTRL, FLD_INPUT_MODE, _p_registers->Set_Field(FLD_INPUT_MODE, INPUT_MODE_CVBS_0));

        // Set some bits in AFE_CTRL so that channel 2 or 3 is ready to receive audio
        // Clear clamp for channels 2 and 3      (bit 16-17)
        // Clear droop comp                      (bit 19-20)
        // Set VGA_SEL (for audio control)       (bit 7-8)
        _p_registers->readDword(AFE_CTRL, &value);
        
        value |= FLD_VGA_SEL_CH3 | FLD_VGA_SEL_CH2;

        _p_registers->writeDword(AFE_CTRL, value);        

        break;
    }
    
    // Set raw VBI mode
    _p_registers->readModifyWriteDword(OUT_CTRL1,FLD_VBIHACTRAW_EN, _p_registers->Set_Field(FLD_VBIHACTRAW_EN, 1) );
        
    _p_registers->unlock();

    // MAE Restores any default adjustments required after hitting the MODE_CTRL registers
    do_MODE_CTRL_overrides();
}

/////////////////////////////////////////////////////////////////////////////////////////
VOID Thresher::setVideoMode(VIDEO_MODE video_mode)
{
    _video_mode = video_mode;