📄 yc2440main.c
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#include "def.h"
#include "2410addr.h"
#include "2410lib.h"
#include "2410slib.h"
#include "uart.h"
#include "timer.h"
#include "led.h"
#include "timer.h"
#define DM9000_ID 0x90000A46
#define DM9000_PKT_MAX 1536 /* Received packet max size */
#define DM9000_PKT_RDY 0x01 /* Packet ready to receive */
/* although the registers are 16 bit, they are 32-bit aligned.
*/
#define DM9000_NCR 0x00
#define DM9000_NSR 0x01
#define DM9000_TCR 0x02
#define DM9000_TSR1 0x03
#define DM9000_TSR2 0x04
#define DM9000_RCR 0x05
#define DM9000_RSR 0x06
#define DM9000_ROCR 0x07
#define DM9000_BPTR 0x08
#define DM9000_FCTR 0x09
#define DM9000_FCR 0x0A
#define DM9000_EPCR 0x0B
#define DM9000_EPAR 0x0C
#define DM9000_EPDRL 0x0D
#define DM9000_EPDRH 0x0E
#define DM9000_WCR 0x0F
#define DM9000_PAR 0x10
#define DM9000_MAR 0x16
#define DM9000_GPCR 0x1e
#define DM9000_GPR 0x1f
#define DM9000_TRPAL 0x22
#define DM9000_TRPAH 0x23
#define DM9000_RWPAL 0x24
#define DM9000_RWPAH 0x25
#define DM9000_VIDL 0x28
#define DM9000_VIDH 0x29
#define DM9000_PIDL 0x2A
#define DM9000_PIDH 0x2B
#define DM9000_CHIPR 0x2C
#define DM9000_SMCR 0x2F
#define DM9000_PHY 0x40 /* PHY address 0x01 */
#define DM9000_MRCMDX 0xF0
#define DM9000_MRCMD 0xF2
#define DM9000_MRRL 0xF4
#define DM9000_MRRH 0xF5
#define DM9000_MWCMDX 0xF6
#define DM9000_MWCMD 0xF8
#define DM9000_MWRL 0xFA
#define DM9000_MWRH 0xFB
#define DM9000_TXPLL 0xFC
#define DM9000_TXPLH 0xFD
#define DM9000_ISR 0xFE
#define DM9000_IMR 0xFF
#define NCR_EXT_PHY (1<<7)
#define NCR_WAKEEN (1<<6)
#define NCR_FCOL (1<<4)
#define NCR_FDX (1<<3)
#define NCR_LBK (3<<1)
#define NCR_RST (1<<0)
#define NSR_SPEED (1<<7)
#define NSR_LINKST (1<<6)
#define NSR_WAKEST (1<<5)
#define NSR_TX2END (1<<3)
#define NSR_TX1END (1<<2)
#define NSR_RXOV (1<<1)
#define TCR_TJDIS (1<<6)
#define TCR_EXCECM (1<<5)
#define TCR_PAD_DIS2 (1<<4)
#define TCR_CRC_DIS2 (1<<3)
#define TCR_PAD_DIS1 (1<<2)
#define TCR_CRC_DIS1 (1<<1)
#define TCR_TXREQ (1<<0)
#define TSR_TJTO (1<<7)
#define TSR_LC (1<<6)
#define TSR_NC (1<<5)
#define TSR_LCOL (1<<4)
#define TSR_COL (1<<3)
#define TSR_EC (1<<2)
#define RCR_WTDIS (1<<6)
#define RCR_DIS_LONG (1<<5)
#define RCR_DIS_CRC (1<<4)
#define RCR_ALL (1<<3)
#define RCR_RUNT (1<<2)
#define RCR_PRMSC (1<<1)
#define RCR_RXEN (1<<0)
#define RSR_RF (1<<7)
#define RSR_MF (1<<6)
#define RSR_LCS (1<<5)
#define RSR_RWTO (1<<4)
#define RSR_PLE (1<<3)
#define RSR_AE (1<<2)
#define RSR_CE (1<<1)
#define RSR_FOE (1<<0)
#define FCTR_HWOT(ot) (( ot & 0xf ) << 4 )
#define FCTR_LWOT(ot) ( ot & 0xf )
#define IMR_PAR (1<<7)
#define IMR_ROOM (1<<3)
#define IMR_ROM (1<<2)
#define IMR_PTM (1<<1)
#define IMR_PRM (1<<0)
U32 Console_Uart = 0;
U32 Console_Baud = 115200;
static void cal_cpu_bus_clk(void)
{
U32 val;
U8 m, p, s;
val = rMPLLCON;
m = (val>>12)&0xff;
p = (val>>4)&0x3f;
s = val&3;
SYS_FCLK = ((m+8)*(FIN/100)*2)/((p+2)*(1<<s))*100;
val = rCLKDIVN;
m = (val>>1)&3;
p = val&1;
val = rCAMDIVN;
s = val>>8;
switch (m) {
case 0:
SYS_HCLK = SYS_FCLK;
break;
case 1:
SYS_HCLK = SYS_FCLK>>1;
break;
case 2:
if(s&2)
SYS_HCLK = SYS_FCLK>>3;
else
SYS_HCLK = SYS_FCLK>>2;
break;
case 3:
if(s&1)
SYS_HCLK = SYS_FCLK/6;
else
SYS_HCLK = SYS_FCLK/3;
break;
}
if(p)
SYS_PCLK = SYS_HCLK>>1;
else
SYS_PCLK = SYS_HCLK;
rUPLLCON = (56<<12) | (2<<4) | 2;
}
typedef unsigned char u8;
typedef unsigned short u16;
typedef unsigned int u32;
#define DM9000_outb(d,r) ( *(volatile u8 *)r = d )
#define DM9000_outw(d,r) ( *(volatile u16 *)r = d )
#define DM9000_outl(d,r) ( *(volatile u32 *)r = d )
#define DM9000_inb(r) (*(volatile u8 *)r)
#define DM9000_inw(r) (*(volatile u16 *)r)
#define DM9000_inl(r) (*(volatile u32 *)r)
#define CONFIG_DM9000_BASE 0x18000300 /* on bank_3(nGCS3), see UTU2440 schematic */
#define DM9000_IO 0x18000300
#define DM9000_DATA 0x18000304 /* LADDR2, see UTU2440 schematic */
volatile unsigned short *g_pusDm9kIo;
volatile unsigned short *g_pusDm9kData;
static u8
DM9000_ior(int reg)
{
DM9000_outb(reg, DM9000_IO);
return DM9000_inb(DM9000_DATA);
}
/*
Write a byte to I/O port
*/
static void
DM9000_iow(int reg, u8 value)
{
DM9000_outb(reg, DM9000_IO);
DM9000_outb(value, DM9000_DATA);
}
void dm9000_reset(void)
{
Uart_Printf("resetting DM9000\n");
/* Reset DM9000,
see DM9000 Application Notes V1.22 Jun 11, 2004 page 29 */
/* DEBUG: Make all GPIO pins outputs */
DM9000_iow(DM9000_GPCR, 0x0F);
/* Step 1: Power internal PHY by writing 0 to GPIO0 pin */
DM9000_iow(DM9000_GPR, 0);
/* Step 2: Software reset */
DM9000_iow(DM9000_NCR, 3);
do {
Uart_Printf("resetting the DM9000, 1st reset\n");
Delay(25); /* Wait at least 20 us */
} while (DM9000_ior(DM9000_NCR) & 1);
DM9000_iow(DM9000_NCR, 0);
DM9000_iow(DM9000_NCR, 3); /* Issue a second reset */
do {
Uart_Printf("resetting the DM9000, 2nd reset\n");
Delay(25); /* Wait at least 20 us */
} while (DM9000_ior(DM9000_NCR) & 1);
/* Check whether the ethernet controller is present */
if ((DM9000_ior(DM9000_PIDL) != 0x0) ||
(DM9000_ior(DM9000_PIDH) != 0x90))
Uart_Printf("ERROR: resetting DM9000 -> not responding\n");
}
/*
Read a word from phyxcer
*/
static u16
phy_read(int reg)
{
u16 val;
/* Fill the phyxcer register into REG_0C */
DM9000_iow(DM9000_EPAR, DM9000_PHY | reg);
DM9000_iow(DM9000_EPCR, 0xc); /* Issue phyxcer read command */
Delay(100); /* Wait read complete */
DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer read command */
val = (DM9000_ior(DM9000_EPDRH) << 8) | DM9000_ior(DM9000_EPDRL);
/* The read data keeps on REG_0D & REG_0E */
Uart_Printf("phy_read(0x%x): 0x%x\n", reg, val);
return val;
}
/*
Write a word to phyxcer
*/
static void
phy_write(int reg, u16 value)
{
/* Fill the phyxcer register into REG_0C */
DM9000_iow(DM9000_EPAR, DM9000_PHY | reg);
/* Fill the written data into REG_0D & REG_0E */
DM9000_iow(DM9000_EPDRL, (value & 0xff));
DM9000_iow(DM9000_EPDRH, ((value >> 8) & 0xff));
DM9000_iow(DM9000_EPCR, 0xa); /* Issue phyxcer write command */
Delay(500); /* Wait write complete */
DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer write command */
Uart_Printf("phy_write(reg:0x%x, value:0x%x)\n", reg, value);
}
int
dm9000_probe(void)
{
u32 id_val;
id_val = DM9000_ior(DM9000_VIDL);
id_val |= DM9000_ior(DM9000_VIDH) << 8;
id_val |= DM9000_ior(DM9000_PIDL) << 16;
id_val |= DM9000_ior(DM9000_PIDH) << 24;
if (id_val == DM9000_ID) {
Uart_Printf("dm9000 i/o: 0x%x, id: 0x%x \n", CONFIG_DM9000_BASE,
id_val);
return 0;
} else {
Uart_Printf("dm9000 not found at 0x%08x id: 0x%08x\n",
CONFIG_DM9000_BASE, id_val);
return -1;
}
}
static void
identify_nic(void)
{
u16 phy_reg3;
DM9000_iow(DM9000_NCR, NCR_EXT_PHY);
phy_reg3 = phy_read(3);
switch (phy_reg3 & 0xfff0) {
case 0xb900:
if (phy_read(31) == 0x4404) {
Uart_Printf("found homerun NIC\n");
} else {
Uart_Printf("found longrun NIC\n");
}
break;
default:
break;
}
DM9000_iow(DM9000_NCR, 0);
}
static void
set_PHY_mode(void)
{
u16 phy_reg4 = 0x01e1, phy_reg0 = 0x1000;
phy_reg4 = 0x101;
phy_reg0 = 0x3100;
phy_write(4, phy_reg4); /* Set PHY media mode */
phy_write(0, phy_reg0); /* Tmp */
DM9000_iow(DM9000_GPCR, 0x01); /* Let GPIO0 output */
DM9000_iow(DM9000_GPR, 0x00); /* Enable PHY */
}
/* Initilize dm9000 board
*/
int
eth_init()
{
int i, oft, lnk;
u8 io_mode;
unsigned char bi_enetaddr[6]={0x01,0x33,0x22,0x33,0x22,0x33};
Uart_Printf("eth_init()\n");
/* RESET device */
dm9000_reset();
dm9000_probe();
/* Auto-detect 8/16/32 bit mode, ISR Bit 6+7 indicate bus width */
io_mode = DM9000_ior(DM9000_ISR) >> 6;
switch (io_mode) {
case 0x0: /* 16-bit mode */
Uart_Printf("DM9000: running in 16 bit mode\n");
break;
case 0x01: /* 32-bit mode */
Uart_Printf("DM9000: running in 32 bit mode\n");
break;
case 0x02: /* 8 bit mode */
Uart_Printf("DM9000: running in 8 bit mode\n");
break;
default:
/* Assume 8 bit mode, will probably not work anyway */
Uart_Printf("DM9000: Undefined IO-mode:0x%x\n", io_mode);
break;
}
/* NIC Type: FASTETHER, HOMERUN, LONGRUN */
identify_nic();
/* GPIO0 on pre-activate PHY */
DM9000_iow(DM9000_GPR, 0x00); /*REG_1F bit0 activate phyxcer */
/* Set PHY */
set_PHY_mode();
/* Program operating register, only intern phy supported by now */
DM9000_iow(DM9000_NCR, 0x0);
/* TX Polling clear */
DM9000_iow(DM9000_TCR, 0);
/* Less 3Kb, 200us */
DM9000_iow(DM9000_BPTR, 0x3f);
/* Flow Control : High/Low Water */
DM9000_iow(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8));
/* SH FIXME: This looks strange! Flow Control */
DM9000_iow(DM9000_FCR, 0x0);
/* Special Mode */
DM9000_iow(DM9000_SMCR, 0);
/* clear TX status */
DM9000_iow(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END);
/* Clear interrupt status */
DM9000_iow(DM9000_ISR, 0x0f);
/* Set Node address */
Uart_Printf("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",bi_enetaddr[0],
bi_enetaddr[1], bi_enetaddr[2], bi_enetaddr[3],
bi_enetaddr[4], bi_enetaddr[5]);
for (i = 0, oft = 0x10; i < 6; i++, oft++)
DM9000_iow(oft, bi_enetaddr[i]);
for (i = 0, oft = 0x16; i < 8; i++, oft++)
DM9000_iow(oft, 0xff);
/* read back mac, just to be sure */
for (i = 0, oft = 0x10; i < 6; i++, oft++)
Uart_Printf("%02x:", DM9000_ior(oft));
Uart_Printf("\n");
/* Activate DM9000 */
/* RX enable */
DM9000_iow(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN);
/* Enable TX/RX interrupt mask */
DM9000_iow(DM9000_IMR, IMR_PAR);
//$$$$$$ Daniel modified below. 2008-10-08
#if 0
/* used for MII interface */
i = 0;
while (!(phy_read(1) & 0x20)) { /* autonegation complete bit */
udelay(1000);
i++;
if (i == 10000) {
Uart_Printf("could not establish link\n");
return 0;
}
}
#endif
//$$$$$$ Daniel modified above. 2008-10-08
/* see what we've got */
lnk = phy_read(17) >> 12;
Uart_Printf("operating at ");
switch (lnk) {
case 1:
Uart_Printf("10M half duplex ");
break;
case 2:
Uart_Printf("10M full duplex ");
break;
case 4:
Uart_Printf("100M half duplex ");
break;
case 8:
Uart_Printf("100M full duplex ");
break;
default:
Uart_Printf("unknown: %d ", lnk);
break;
}
Uart_Printf("mode\n");
return 0;
}
int Main(U32 RstStat)
{
int iKey=0;
ChangeMPllValue(92,1,1); //400MHZ
SetClockDivider(2,1); //fclk:hclk:pclk=1:4:8
cal_cpu_bus_clk();
rGPHCON=(rGPHCON&0x3ffff)|(0x0a<<18);
rMISCCR=(rMISCCR&0x0f)|(0x02<<4);
rMISCCR=(rMISCCR&0x0f)|(0x03<<4);
rMISCCR=(rMISCCR&0x0f)|(0x04<<4);
Port_Init();
Isr_Init();
Uart_Init(0, Console_Baud);
Uart_Select(Console_Uart);
EnableModuleClock(CLOCK_ALL);
//初始化IO
g_pusDm9kIo=(volatile u16 *)DM9000_IO;
g_pusDm9kData=(volatile u16 *)DM9000_DATA;
//
while(1)
{
Uart_Printf("Menu:\n");
Uart_Printf(" r -- Reset dm9000\n");
Uart_Printf(" g -- Get dm9000 ID\n");
Uart_Printf(" i -- Init dm9000\n");
Uart_Printf(" 1 -- Write to 0x%x with 0x5a5a5a5a\n",g_pusDm9kIo);
Uart_Printf(" 2 -- Write to 0x%x with 0x00000000\n",g_pusDm9kIo);
Uart_Printf(" 3 -- Write to 0x%x with 0xffffffff\n",g_pusDm9kIo);
Uart_Printf(" 4 -- Write to 0x%x with 0xa5a5a5a5\n",g_pusDm9kIo);
Uart_Printf(" 5 -- Write to 0x%x with 0x55555555\n",g_pusDm9kIo);
Uart_Printf(" 6 -- Write to 0x%x with 0xaaaaaaaa\n",g_pusDm9kIo);
Uart_Printf(" 7 -- Write to 0x%x with 0xaaaaaaaa\n",g_pusDm9kData);
iKey=Uart_Getch();
switch(iKey)
{
case 'r':
{
Uart_Printf("Reset dm9000\n");
dm9000_reset();
break;
}
case 'g':
{
Uart_Printf("Get dm9000 ID\n");
dm9000_probe();
break;
}
case 'i':
{
Uart_Printf("Init dm9000\n");
eth_init();
break;
}
case '1':
{
while(1)
{
int iKeyPress=0;
*g_pusDm9kIo=0x5a5a5a5a;
iKeyPress=Uart_GetKey();
if(iKeyPress!=0)
{
break;
}
}
break;
}
case '2':
{
while(1)
{
int iKeyPress=0;
*g_pusDm9kIo=0x0;
iKeyPress=Uart_GetKey();
if(iKeyPress!=0)
{
break;
}
}
break;
}
case '3':
{
while(1)
{
int iKeyPress=0;
*g_pusDm9kIo=0xffffffff;
iKeyPress=Uart_GetKey();
if(iKeyPress!=0)
{
break;
}
}
break;
}
case '4':
{
while(1)
{
int iKeyPress=0;
*g_pusDm9kIo=0xa5a5a5a5;
iKeyPress=Uart_GetKey();
if(iKeyPress!=0)
{
break;
}
}
break;
}
case '5':
{
while(1)
{
int iKeyPress=0;
*g_pusDm9kIo=0x55555555;
iKeyPress=Uart_GetKey();
if(iKeyPress!=0)
{
break;
}
}
break;
}
case '6':
{
while(1)
{
int iKeyPress=0;
*g_pusDm9kIo=0xaaaaaaaa;
iKeyPress=Uart_GetKey();
if(iKeyPress!=0)
{
break;
}
}
break;
}
case '7':
{
while(1)
{
int iKeyPress=0;
*g_pusDm9kData=0xaaaaaaaa;
iKeyPress=Uart_GetKey();
if(iKeyPress!=0)
{
break;
}
}
break;
}
}
}
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