📄 ultrasonic.s43
字号:
TAX_ISR; Common ISR for CCR1-4 and overflow
;******************************************************************************
add.w &TAIV,PC ; Add TA interrupt offset to PC
reti ; CCR0 - no source
jmp CCR1_ISR ; CCR1
reti ; CCR2
reti ; CCR3
reti ; CCR4
TA_over reti ; Timer_A overflow
CCR1_ISR bic.w #CCIFG,&CCTL1
bic.w #LPM0,0(SP) ; Exit LPM0 on reti
reti ;
;******************************************************************************
Display ;Subroutine to Display values DIGIT1 & DIGIT2
;CPU Registers used R15, R14, R13 and R12, not saved
;******************************************************************************
mov.w #LCDM1,R15 ; R15 points to first LCD location
mov.b DIGITS,R14 ; LSD value moved to R14
OutLCD mov.b R14,R13 ; Copy value in R14 to R13
rra.b R13 ; Right Shift
rra.b R13 ; four times to
rra.b R13 ; swap
rra.b R13 ; nibbles
and.b #0Fh,R14 ; low nibble now in R14
and.b #0Fh,R13 ; high nibble now in R13
mov.b LCD_Tab(R14),R12 ; Low nibble to LCD digit 1
mov.b R12,0(R15) ; Low nibble segments a & b to LCD
rra.w R12
inc.b R15
mov.b R12,0(R15) ; Low nibble segments c & d to LCD
rra.w R12
inc.b R15
mov.b R12,0(R15) ; Low nibble segments e & f to LCD
rra.w R12
inc.b R15
mov.b R12,0(R15) ; Low nibble segments g & h to LCD
rra.w R12
inc.b R15
mov.b LCD_Tab(R13),R12 ; High nibble to LCD digit 2
mov.b R12,0(R15) ; High nibble segments a & b to LCD
rra.w R12
inc.b R15
mov.b R12,0(R15) ; High nibble segments c & d to LCD
rra.w R12
inc.b R15
mov.b R12,0(R15) ; High nibble segments e & f to LCD
rra.w R12
inc.b R15
mov.b R12,0(R15) ; High nibble segments g & h to LCD
rra.w R12
ret
;******************************************************************************
; LCD Type Definition
;******************************************************************************
;Segments definition
a equ 001h
b equ 010h
c equ 002h
d equ 020h
e equ 004h
f equ 040h
g equ 008h
h equ 080h
Blank equ 000h
LCD_Tab db a+b+c+d+e+f ; Displays "0"
db b+c ; Displays "1"
db a+b+d+e+g ; Displays "2"
db a+b+c+d+g ; Displays "3"
db b+c+f+g ; Displays "4"
db a+c+d+f+g ; Displays "5"
db a+c+d+e+f+g ; Displays "6"
db a+b+c ; Displays "7"
db a+b+c+d+e+f+g ; Displays "8"
db a+b+c+d+f+g ; Displays "9"
db a+b+c+e+f+g ; Displays "A"
db Blank ; Displays Blank
db a+d+e+f ; Displays "C"
db b+c+d+e+g ; Displays "D" d
db a+d+e+f+g ; Displays "E"
db a+e+f+g ; Displays "F"
;******************************************************************************
Delay; Software delay
;******************************************************************************
push #0FFFFh ; Delay to TOS
DL1 dec.w 0(SP) ; Decrement TOS
jnz DL1 ; Delay over?
incd SP ; Clean TOS
ret ; Return from subroutine
;******************************************************************************
Math_calc; calculation subroutine
;******************************************************************************
mov.w #0h, DIGITS ; Initialise DIGIT to 0
cmp.w #0h, Result ; Check if Result count=0
jeq calc_over ; Exit if 0
call #Mul100 ; Multiply Result count by 100
call #Divide ; Divide the result with #06d
call #Hex2bcd ; Convert 16bit binary to BCD number
; Result xx.xx
calc_over ret ; Return from subroutine
;******************************************************************************
Mul100 ;subroutine for multiplying Result with 100d
;inputs Result 16bit and constant 64h (100d) 16bit
;output 32bit htX100_msw & htX100_lsw
;******************************************************************************
mov.w #100,IROP1 ; Load IROP1 with 100 (multiplier)
mpyu clr.w htX100_lsw ; Clear buffer for least
; significant word
clr.w htX100_msw ; Clear buffer for most
; significant word
macu clr.w IROP2M ; Clear multiplier high word
L$002 bit.w #1,IROP1 ; Test actual bit
jz L$01 ; If 0: do nothing
add.w Result,htX100_lsw ; If 1: Add multiplier to Result
addc.w IROP2M,htX100_msw ;
L$01 rla.w Result ; Multiplier X 2
rlc.w IROP2M ;
rrc.w IROP1 ; Next bit to test
jnz L$002 ; If bit in carry : finished
ret
;******************************************************************************
Divide ;Subroutine for 32/16 bits division
;inputs 32bit htX100_msw & htX100_lsw and #06 16bit, output DIGIT 16bit
;******************************************************************************
clr.w DIGITS ; Clear buffer to hold new Result
mov.w #17,IRBT ; Initialize loop counter
div1 cmp.w #06,htX100_msw ; Compare divisor with dividend high word
jlo div2 ; If less : jump to div2
sub.w #06,htX100_msw ; Subtract 6 from high word
div2 rlc.w DIGITS ; Rotate result left through carry 1 bit
jc div4 ; If carry set: finished
dec.w IRBT ; Decrement bit counter
jz div3 ; If counter = 0 : finished
rla.w htX100_lsw ; Dividend X 2
rlc.w htX100_msw ;
jnc div1 ; If carry not set jump to step div1
sub.w #06,htX100_msw ; Subtract 6 from high word
setc ; Set carry
jmp div2 ; Jump to repeat
div3 clrc ; Clear carry
div4 ret ; Return from subroutine
;******************************************************************************
Hex2bcd ;Subroutine for converting 16bit hexadecimal value to BCD value
;input in DIGITS 16bit hexadecimal, output in DIGITS 16bit BCD
;******************************************************************************
mov #16,r9 ; R9 no of bits
clr r8 ; Clear R8
clr r7 ; Clear R7
L$1 rla DIGITS ; Rotate left arithmetic DIGITS
dadd r7,r7 ; Add source and carry decimally
dadd r8,r8 ; to destination
dec r9 ; Decrement bit counter
jnz L$1 ; Is 16 bits over ?
mov r7,DIGITS ; Result in DIGITS
ret ; Return from subroutine
;******************************************************************************
COMMON INTVEC ; MSP430x41x Interrupt vectors
;******************************************************************************
ORG BASICTIMER_VECTOR
BT_VEC DW BT_ISR ; Basic Timer Vector
ORG TIMERA1_VECTOR ; Timer_AX Vector
TIMA_VEC DW TAX_ISR ;
ORG RESET_VECTOR
RESET_VEC DW RESET ; POR, ext. Reset, Watchdog
;******************************************************************************
END
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -