📄 dds_vhdl.map.rpt
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; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ;
; INIT_FILE ; LUT10X10.MIF ; Untyped ;
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
; MAXIMUM_DEPTH ; 0 ; Untyped ;
; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ;
; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ;
; ENABLE_ECC ; FALSE ; Untyped ;
; DEVICE_FAMILY ; Cyclone ; Untyped ;
; CBXI_PARAMETER ; altsyncram_u631 ; Untyped ;
+------------------------------------+----------------------+-----------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-----------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: sin_rom:u6|altsyncram:altsyncram_component ;
+------------------------------------+----------------------+-----------------------------+
; Parameter Name ; Value ; Type ;
+------------------------------------+----------------------+-----------------------------+
; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; WIDTH_BYTEENA ; 1 ; Untyped ;
; OPERATION_MODE ; ROM ; Untyped ;
; WIDTH_A ; 10 ; Signed Integer ;
; WIDTHAD_A ; 10 ; Signed Integer ;
; NUMWORDS_A ; 1024 ; Signed Integer ;
; OUTDATA_REG_A ; CLOCK0 ; Untyped ;
; ADDRESS_ACLR_A ; NONE ; Untyped ;
; OUTDATA_ACLR_A ; NONE ; Untyped ;
; WRCONTROL_ACLR_A ; NONE ; Untyped ;
; INDATA_ACLR_A ; NONE ; Untyped ;
; BYTEENA_ACLR_A ; NONE ; Untyped ;
; WIDTH_B ; 1 ; Untyped ;
; WIDTHAD_B ; 1 ; Untyped ;
; NUMWORDS_B ; 1 ; Untyped ;
; INDATA_REG_B ; CLOCK1 ; Untyped ;
; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
; ADDRESS_REG_B ; CLOCK1 ; Untyped ;
; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
; INDATA_ACLR_B ; NONE ; Untyped ;
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
; ADDRESS_ACLR_B ; NONE ; Untyped ;
; OUTDATA_ACLR_B ; NONE ; Untyped ;
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
; BYTEENA_ACLR_B ; NONE ; Untyped ;
; WIDTH_BYTEENA_A ; 1 ; Signed Integer ;
; WIDTH_BYTEENA_B ; 1 ; Untyped ;
; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
; BYTE_SIZE ; 8 ; Untyped ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;
; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ;
; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ;
; INIT_FILE ; LUT10X10.MIF ; Untyped ;
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
; MAXIMUM_DEPTH ; 0 ; Untyped ;
; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ;
; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ;
; ENABLE_ECC ; FALSE ; Untyped ;
; DEVICE_FAMILY ; Cyclone ; Untyped ;
; CBXI_PARAMETER ; altsyncram_u631 ; Untyped ;
+------------------------------------+----------------------+-----------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
Info: Processing started: Sun Aug 10 19:36:07 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DDS_VHDL -c DDS_VHDL
Info: Found 2 design units, including 1 entities, in source file ADDER32B.vhd
Info: Found design unit 1: ADDER32B-behav
Info: Found entity 1: ADDER32B
Info: Found 2 design units, including 1 entities, in source file ADDER10B.vhd
Info: Found design unit 1: ADDER10B-behav
Info: Found entity 1: ADDER10B
Info: Found 2 design units, including 1 entities, in source file REG32B.vhd
Info: Found design unit 1: REG32B-behav
Info: Found entity 1: REG32B
Info: Found 2 design units, including 1 entities, in source file REG10B.vhd
Info: Found design unit 1: REG10B-behav
Info: Found entity 1: REG10B
Info: Found 2 design units, including 1 entities, in source file sin_rom.vhd
Info: Found design unit 1: sin_rom-SYN
Info: Found entity 1: sin_rom
Info: Found 2 design units, including 1 entities, in source file DDS_VHDL.vhd
Info: Found design unit 1: DDS_VHDL-one
Info: Found entity 1: DDS_VHDL
Info: Elaborating entity "DDS_VHDL" for the top level hierarchy
Info: Elaborating entity "ADDER32B" for hierarchy "ADDER32B:u1"
Info: Elaborating entity "REG32B" for hierarchy "REG32B:u2"
Info: Elaborating entity "sin_rom" for hierarchy "sin_rom:u3"
Info: Found 1 design units, including 1 entities, in source file ../altera/71/quartus/libraries/megafunctions/altsyncram.tdf
Info: Found entity 1: altsyncram
Info: Elaborating entity "altsyncram" for hierarchy "sin_rom:u3|altsyncram:altsyncram_component"
Info: Elaborated megafunction instantiation "sin_rom:u3|altsyncram:altsyncram_component"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_u631.tdf
Info: Found entity 1: altsyncram_u631
Info: Elaborating entity "altsyncram_u631" for hierarchy "sin_rom:u3|altsyncram:altsyncram_component|altsyncram_u631:auto_generated"
Info: Elaborating entity "ADDER10B" for hierarchy "ADDER10B:u4"
Info: Elaborating entity "REG10B" for hierarchy "REG10B:u5"
Info: Duplicate registers merged to single register
Info: Duplicate register "REG32B:u2|DOUT[18]" merged to single register "REG32B:u2|DOUT[0]"
Info: Duplicate register "REG32B:u2|DOUT[10]" merged to single register "REG32B:u2|DOUT[0]"
Info: Duplicate register "REG32B:u2|DOUT[4]" merged to single register "REG32B:u2|DOUT[0]"
Info: Duplicate register "REG32B:u2|DOUT[16]" merged to single register "REG32B:u2|DOUT[0]"
Info: Duplicate register "REG32B:u2|DOUT[12]" merged to single register "REG32B:u2|DOUT[0]"
Info: Duplicate register "REG32B:u2|DOUT[8]" merged to single register "REG32B:u2|DOUT[0]"
Info: Duplicate register "REG32B:u2|DOUT[19]" merged to single register "REG32B:u2|DOUT[0]"
Info: Duplicate register "REG32B:u2|DOUT[1]" merged to single register "REG32B:u2|DOUT[0]"
Info: Duplicate register "REG32B:u2|DOUT[11]" merged to single register "REG32B:u2|DOUT[0]"
Info: Duplicate register "REG32B:u2|DOUT[5]" merged to single register "REG32B:u2|DOUT[0]"
Info: Duplicate register "REG32B:u2|DOUT[15]" merged to single register "REG32B:u2|DOUT[0]"
Info: Duplicate register "REG32B:u2|DOUT[13]" merged to single register "REG32B:u2|DOUT[0]"
Info: Duplicate register "REG32B:u2|DOUT[7]" merged to single register "REG32B:u2|DOUT[0]"
Info: Duplicate register "REG32B:u2|DOUT[17]" merged to single register "REG32B:u2|DOUT[0]"
Info: Duplicate register "REG32B:u2|DOUT[3]" merged to single register "REG32B:u2|DOUT[0]"
Info: Duplicate register "REG32B:u2|DOUT[9]" merged to single register "REG32B:u2|DOUT[0]"
Info: Duplicate register "REG32B:u2|DOUT[2]" merged to single register "REG32B:u2|DOUT[0]"
Info: Duplicate register "REG32B:u2|DOUT[6]" merged to single register "REG32B:u2|DOUT[0]"
Info: Duplicate register "REG32B:u2|DOUT[14]" merged to single register "REG32B:u2|DOUT[0]"
Warning: Reduced register "REG32B:u2|DOUT[0]" with stuck data_in port to stuck value GND
Info: Implemented 79 device resources after synthesis - the final resource count might be different
Info: Implemented 17 input pins
Info: Implemented 20 output pins
Info: Implemented 22 logic cells
Info: Implemented 20 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
Info: Allocated 150 megabytes of memory during processing
Info: Processing ended: Sun Aug 10 19:36:10 2008
Info: Elapsed time: 00:00:03
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