📄 dds_vhdl.map.rpt
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; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+-------+
; Resource ; Usage ;
+---------------------------------------------+-------+
; Total logic elements ; 22 ;
; -- Combinational with no register ; 0 ;
; -- Register only ; 2 ;
; -- Combinational with a register ; 20 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 0 ;
; -- 3 input functions ; 14 ;
; -- 2 input functions ; 6 ;
; -- 1 input functions ; 0 ;
; -- 0 input functions ; 0 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 4 ;
; -- arithmetic mode ; 18 ;
; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 0 ;
; -- asynchronous clear/load mode ; 0 ;
; ; ;
; Total registers ; 22 ;
; Total logic cells in carry chains ; 20 ;
; I/O pins ; 37 ;
; Total memory bits ; 20480 ;
; Maximum fan-out node ; CLK ;
; Maximum fan-out ; 42 ;
; Total fan-out ; 318 ;
; Average fan-out ; 4.03 ;
+---------------------------------------------+-------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+-------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+-------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------+--------------+
; |DDS_VHDL ; 22 (0) ; 22 ; 20480 ; 37 ; 0 ; 0 (0) ; 2 (0) ; 20 (0) ; 20 (0) ; 0 (0) ; |DDS_VHDL ; work ;
; |REG10B:u5| ; 10 (10) ; 10 ; 0 ; 0 ; 0 ; 0 (0) ; 2 (2) ; 8 (8) ; 8 (8) ; 0 (0) ; |DDS_VHDL|REG10B:u5 ; work ;
; |REG32B:u2| ; 12 (12) ; 12 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 12 (12) ; 12 (12) ; 0 (0) ; |DDS_VHDL|REG32B:u2 ; work ;
; |sin_rom:u3| ; 0 (0) ; 0 ; 10240 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |DDS_VHDL|sin_rom:u3 ; work ;
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 ; 10240 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |DDS_VHDL|sin_rom:u3|altsyncram:altsyncram_component ; work ;
; |altsyncram_u631:auto_generated| ; 0 (0) ; 0 ; 10240 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |DDS_VHDL|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_u631:auto_generated ; work ;
; |sin_rom:u6| ; 0 (0) ; 0 ; 10240 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |DDS_VHDL|sin_rom:u6 ; work ;
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 ; 10240 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |DDS_VHDL|sin_rom:u6|altsyncram:altsyncram_component ; work ;
; |altsyncram_u631:auto_generated| ; 0 (0) ; 0 ; 10240 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |DDS_VHDL|sin_rom:u6|altsyncram:altsyncram_component|altsyncram_u631:auto_generated ; work ;
+-------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+--------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+-------+--------------+
; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
+--------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+-------+--------------+
; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|ALTSYNCRAM ; AUTO ; ROM ; 1024 ; 10 ; -- ; -- ; 10240 ; LUT10X10.MIF ;
; sin_rom:u6|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|ALTSYNCRAM ; AUTO ; ROM ; 1024 ; 10 ; -- ; -- ; 10240 ; LUT10X10.MIF ;
+--------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+-------+--------------+
+---------------------------------------------------------------------------------+
; Registers Removed During Synthesis ;
+----------------------------------------+----------------------------------------+
; Register name ; Reason for Removal ;
+----------------------------------------+----------------------------------------+
; u2/DOUT[1..19] ; Merged with u2/DOUT[0] ;
; u2/DOUT[0] ; Stuck at GND due to stuck port data_in ;
; Total Number of Removed Registers = 20 ; ;
+----------------------------------------+----------------------------------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 22 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+--------------------------------------------------------------------------------------------------+
; Source assignments for sin_rom:u3|altsyncram:altsyncram_component|altsyncram_u631:auto_generated ;
+---------------------------------+--------------------+------+------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+------------------------------------+
+--------------------------------------------------------------------------------------------------+
; Source assignments for sin_rom:u6|altsyncram:altsyncram_component|altsyncram_u631:auto_generated ;
+---------------------------------+--------------------+------+------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+------------------------------------+
+-----------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: sin_rom:u3|altsyncram:altsyncram_component ;
+------------------------------------+----------------------+-----------------------------+
; Parameter Name ; Value ; Type ;
+------------------------------------+----------------------+-----------------------------+
; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; WIDTH_BYTEENA ; 1 ; Untyped ;
; OPERATION_MODE ; ROM ; Untyped ;
; WIDTH_A ; 10 ; Signed Integer ;
; WIDTHAD_A ; 10 ; Signed Integer ;
; NUMWORDS_A ; 1024 ; Signed Integer ;
; OUTDATA_REG_A ; CLOCK0 ; Untyped ;
; ADDRESS_ACLR_A ; NONE ; Untyped ;
; OUTDATA_ACLR_A ; NONE ; Untyped ;
; WRCONTROL_ACLR_A ; NONE ; Untyped ;
; INDATA_ACLR_A ; NONE ; Untyped ;
; BYTEENA_ACLR_A ; NONE ; Untyped ;
; WIDTH_B ; 1 ; Untyped ;
; WIDTHAD_B ; 1 ; Untyped ;
; NUMWORDS_B ; 1 ; Untyped ;
; INDATA_REG_B ; CLOCK1 ; Untyped ;
; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
; ADDRESS_REG_B ; CLOCK1 ; Untyped ;
; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
; INDATA_ACLR_B ; NONE ; Untyped ;
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
; ADDRESS_ACLR_B ; NONE ; Untyped ;
; OUTDATA_ACLR_B ; NONE ; Untyped ;
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
; BYTEENA_ACLR_B ; NONE ; Untyped ;
; WIDTH_BYTEENA_A ; 1 ; Signed Integer ;
; WIDTH_BYTEENA_B ; 1 ; Untyped ;
; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
; BYTE_SIZE ; 8 ; Untyped ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;
; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ;
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