prev_cmp_dds_vhdl.map.qmsg

dds移相信号发生器 VHDL语言代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 10 19:35:38 2008 " "Info: Processing started: Sun Aug 10 19:35:38 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off DDS_VHDL -c DDS_VHDL " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DDS_VHDL -c DDS_VHDL" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ADDER32B.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ADDER32B.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ADDER32B-behav " "Info: Found design unit 1: ADDER32B-behav" {  } { { "ADDER32B.vhd" "" { Text "C:/testlog/ADDER32B.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 ADDER32B " "Info: Found entity 1: ADDER32B" {  } { { "ADDER32B.vhd" "" { Text "C:/testlog/ADDER32B.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ADDER10B.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ADDER10B.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ADDER10B-behav " "Info: Found design unit 1: ADDER10B-behav" {  } { { "ADDER10B.vhd" "" { Text "C:/testlog/ADDER10B.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 ADDER10B " "Info: Found entity 1: ADDER10B" {  } { { "ADDER10B.vhd" "" { Text "C:/testlog/ADDER10B.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "REG32B.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file REG32B.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 REG32B-behav " "Info: Found design unit 1: REG32B-behav" {  } { { "REG32B.vhd" "" { Text "C:/testlog/REG32B.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 REG32B " "Info: Found entity 1: REG32B" {  } { { "REG32B.vhd" "" { Text "C:/testlog/REG32B.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "REG10B.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file REG10B.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 REG10B-behav " "Info: Found design unit 1: REG10B-behav" {  } { { "REG10B.vhd" "" { Text "C:/testlog/REG10B.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 REG10B " "Info: Found entity 1: REG10B" {  } { { "REG10B.vhd" "" { Text "C:/testlog/REG10B.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sin_rom.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file sin_rom.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sin_rom-SYN " "Info: Found design unit 1: sin_rom-SYN" {  } { { "sin_rom.vhd" "" { Text "C:/testlog/sin_rom.vhd" 52 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 sin_rom " "Info: Found entity 1: sin_rom" {  } { { "sin_rom.vhd" "" { Text "C:/testlog/sin_rom.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DDS_VHDL.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file DDS_VHDL.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 DDS_VHDL-one " "Info: Found design unit 1: DDS_VHDL-one" {  } { { "DDS_VHDL.vhd" "" { Text "C:/testlog/DDS_VHDL.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 DDS_VHDL " "Info: Found entity 1: DDS_VHDL" {  } { { "DDS_VHDL.vhd" "" { Text "C:/testlog/DDS_VHDL.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Error" "EVRFX_VHDL_FORMAL_NOT_DECLARED" "clock DDS_VHDL.vhd(49) " "Error (10349): VHDL Association List error at DDS_VHDL.vhd(49): formal \"clock\" does not exist" {  } { { "DDS_VHDL.vhd" "" { Text "C:/testlog/DDS_VHDL.vhd" 49 0 0 } }  } 0 10349 "VHDL Association List error at %2!s!: formal \"%1!s!\" does not exist" 0 0 "" 0}
{ "Error" "EVRFX_VHDL_FORMAL_HAS_NO_VALUE" "inclock DDS_VHDL.vhd(49) " "Error (10346): VHDL error at DDS_VHDL.vhd(49): formal port or parameter \"inclock\" must have actual or default value" {  } { { "DDS_VHDL.vhd" "" { Text "C:/testlog/DDS_VHDL.vhd" 49 0 0 } }  } 0 10346 "VHDL error at %2!s!: formal port or parameter \"%1!s!\" must have actual or default value" 0 0 "" 0}
{ "Info" "IVRFX_VHDL_IS_DECLARED_HERE" "inclock DDS_VHDL.vhd(34) " "Info (10499): VHDL information at DDS_VHDL.vhd(34): object \"inclock\" is declared here" {  } { { "DDS_VHDL.vhd" "" { Text "C:/testlog/DDS_VHDL.vhd" 34 0 0 } }  } 0 10499 "VHDL information at %2!s!: object \"%1!s!\" is declared here" 0 0 "" 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "145 " "Info: Allocated 145 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Error" "EQEXE_END_BANNER_TIME" "Sun Aug 10 19:35:40 2008 " "Error: Processing ended: Sun Aug 10 19:35:40 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:02 " "Error: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}