dds_vhdl.tan.qmsg

dds移相信号发生器 VHDL语言代码

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK memory sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|ram_block1a0~porta_address_reg0 memory sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|q_a\[0\] 256.02 MHz 3.906 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 256.02 MHz between source memory \"sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|ram_block1a0~porta_address_reg0\" and destination memory \"sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|q_a\[0\]\" (period= 3.906 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.323 ns + Longest memory memory " "Info: + Longest memory to memory delay is 3.323 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|ram_block1a0~porta_address_reg0 1 MEM M4K_X17_Y10 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X17_Y10; Fanout = 4; MEM Node = 'sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|ram_block1a0~porta_address_reg0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_u631.tdf" "" { Text "C:/testlog/db/altsyncram_u631.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.323 ns) 3.323 ns sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|q_a\[0\] 2 MEM M4K_X17_Y10 1 " "Info: 2: + IC(0.000 ns) + CELL(3.323 ns) = 3.323 ns; Loc. = M4K_X17_Y10; Fanout = 1; MEM Node = 'sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|q_a\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.323 ns" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|ram_block1a0~porta_address_reg0 sin_rom:u3|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[0] } "NODE_NAME" } } { "db/altsyncram_u631.tdf" "" { Text "C:/testlog/db/altsyncram_u631.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.323 ns ( 100.00 % ) " "Info: Total cell delay = 3.323 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.323 ns" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|ram_block1a0~porta_address_reg0 sin_rom:u3|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.323 ns" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|ram_block1a0~porta_address_reg0 sin_rom:u3|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[0] } { 0.000ns 0.000ns } { 0.000ns 3.323ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.011 ns - Smallest " "Info: - Smallest clock skew is -0.011 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.260 ns + Shortest memory " "Info: + Shortest clock path from clock \"CLK\" to destination memory is 2.260 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns CLK 1 CLK PIN_29 102 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 102; CLK Node = 'CLK'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "DDS_VHDL.vhd" "" { Text "C:/testlog/DDS_VHDL.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.585 ns) + CELL(0.545 ns) 2.260 ns sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|q_a\[0\] 2 MEM M4K_X17_Y10 1 " "Info: 2: + IC(0.585 ns) + CELL(0.545 ns) = 2.260 ns; Loc. = M4K_X17_Y10; Fanout = 1; MEM Node = 'sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|q_a\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.130 ns" { CLK sin_rom:u3|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[0] } "NODE_NAME" } } { "db/altsyncram_u631.tdf" "" { Text "C:/testlog/db/altsyncram_u631.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.675 ns ( 74.12 % ) " "Info: Total cell delay = 1.675 ns ( 74.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.585 ns ( 25.88 % ) " "Info: Total interconnect delay = 0.585 ns ( 25.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.260 ns" { CLK sin_rom:u3|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.260 ns" { CLK CLK~out0 sin_rom:u3|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[0] } { 0.000ns 0.000ns 0.585ns } { 0.000ns 1.130ns 0.545ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.271 ns - Longest memory " "Info: - Longest clock path from clock \"CLK\" to source memory is 2.271 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns CLK 1 CLK PIN_29 102 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 102; CLK Node = 'CLK'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "DDS_VHDL.vhd" "" { Text "C:/testlog/DDS_VHDL.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.585 ns) + CELL(0.556 ns) 2.271 ns sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|ram_block1a0~porta_address_reg0 2 MEM M4K_X17_Y10 4 " "Info: 2: + IC(0.585 ns) + CELL(0.556 ns) = 2.271 ns; Loc. = M4K_X17_Y10; Fanout = 4; MEM Node = 'sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|ram_block1a0~porta_address_reg0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.141 ns" { CLK sin_rom:u3|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_u631.tdf" "" { Text "C:/testlog/db/altsyncram_u631.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.686 ns ( 74.24 % ) " "Info: Total cell delay = 1.686 ns ( 74.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.585 ns ( 25.76 % ) " "Info: Total interconnect delay = 0.585 ns ( 25.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.271 ns" { CLK sin_rom:u3|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.271 ns" { CLK CLK~out0 sin_rom:u3|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|ram_block1a0~porta_address_reg0 } { 0.000ns 0.000ns 0.585ns } { 0.000ns 1.130ns 0.556ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.260 ns" { CLK sin_rom:u3|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.260 ns" { CLK CLK~out0 sin_rom:u3|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[0] } { 0.000ns 0.000ns 0.585ns } { 0.000ns 1.130ns 0.545ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.271 ns" { CLK sin_rom:u3|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.271 ns" { CLK CLK~out0 sin_rom:u3|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|ram_block1a0~porta_address_reg0 } { 0.000ns 0.000ns 0.585ns } { 0.000ns 1.130ns 0.556ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "db/altsyncram_u631.tdf" "" { Text "C:/testlog/db/altsyncram_u631.tdf" 43 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.072 ns + " "Info: + Micro setup delay of destination is 0.072 ns" {  } { { "db/altsyncram_u631.tdf" "" { Text "C:/testlog/db/altsyncram_u631.tdf" 40 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.323 ns" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|ram_block1a0~porta_address_reg0 sin_rom:u3|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.323 ns" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|ram_block1a0~porta_address_reg0 sin_rom:u3|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[0] } { 0.000ns 0.000ns } { 0.000ns 3.323ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.260 ns" { CLK sin_rom:u3|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.260 ns" { CLK CLK~out0 sin_rom:u3|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[0] } { 0.000ns 0.000ns 0.585ns } { 0.000ns 1.130ns 0.545ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.271 ns" { CLK sin_rom:u3|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.271 ns" { CLK CLK~out0 sin_rom:u3|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|ram_block1a0~porta_address_reg0 } { 0.000ns 0.000ns 0.585ns } { 0.000ns 1.130ns 0.556ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "REG10B:u5\|DOUT\[7\] PWORD\[4\] CLK 5.087 ns register " "Info: tsu for register \"REG10B:u5\|DOUT\[7\]\" (data pin = \"PWORD\[4\]\", clock pin = \"CLK\") is 5.087 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.329 ns + Longest pin register " "Info: + Longest pin to register delay is 7.329 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns PWORD\[4\] 1 PIN PIN_80 2 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_80; Fanout = 2; PIN Node = 'PWORD\[4\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { PWORD[4] } "NODE_NAME" } } { "DDS_VHDL.vhd" "" { Text "C:/testlog/DDS_VHDL.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.099 ns) + CELL(0.449 ns) 6.683 ns REG10B:u5\|DOUT\[6\]~46 2 COMB LC_X16_Y13_N4 3 " "Info: 2: + IC(5.099 ns) + CELL(0.449 ns) = 6.683 ns; Loc. = LC_X16_Y13_N4; Fanout = 3; COMB Node = 'REG10B:u5\|DOUT\[6\]~46'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.548 ns" { PWORD[4] REG10B:u5|DOUT[6]~46 } "NODE_NAME" } } { "REG10B.vhd" "" { Text "C:/testlog/REG10B.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.646 ns) 7.329 ns REG10B:u5\|DOUT\[7\] 3 REG LC_X16_Y13_N5 3 " "Info: 3: + IC(0.000 ns) + CELL(0.646 ns) = 7.329 ns; Loc. = LC_X16_Y13_N5; Fanout = 3; REG Node = 'REG10B:u5\|DOUT\[7\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.646 ns" { REG10B:u5|DOUT[6]~46 REG10B:u5|DOUT[7] } "NODE_NAME" } } { "REG10B.vhd" "" { Text "C:/testlog/REG10B.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.230 ns ( 30.43 % ) " "Info: Total cell delay = 2.230 ns ( 30.43 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.099 ns ( 69.57 % ) " "Info: Total interconnect delay = 5.099 ns ( 69.57 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.329 ns" { PWORD[4] REG10B:u5|DOUT[6]~46 REG10B:u5|DOUT[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.329 ns" { PWORD[4] PWORD[4]~out0 REG10B:u5|DOUT[6]~46 REG10B:u5|DOUT[7] } { 0.000ns 0.000ns 5.099ns 0.000ns } { 0.000ns 1.135ns 0.449ns 0.646ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" {  } { { "REG10B.vhd" "" { Text "C:/testlog/REG10B.vhd" 12 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.271 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 2.271 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns CLK 1 CLK PIN_29 102 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 102; CLK Node = 'CLK'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "DDS_VHDL.vhd" "" { Text "C:/testlog/DDS_VHDL.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.594 ns) + CELL(0.547 ns) 2.271 ns REG10B:u5\|DOUT\[7\] 2 REG LC_X16_Y13_N5 3 " "Info: 2: + IC(0.594 ns) + CELL(0.547 ns) = 2.271 ns; Loc. = LC_X16_Y13_N5; Fanout = 3; REG Node = 'REG10B:u5\|DOUT\[7\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.141 ns" { CLK REG10B:u5|DOUT[7] } "NODE_NAME" } } { "REG10B.vhd" "" { Text "C:/testlog/REG10B.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 73.84 % ) " "Info: Total cell delay = 1.677 ns ( 73.84 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.594 ns ( 26.16 % ) " "Info: Total interconnect delay = 0.594 ns ( 26.16 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.271 ns" { CLK REG10B:u5|DOUT[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.271 ns" { CLK CLK~out0 REG10B:u5|DOUT[7] } { 0.000ns 0.000ns 0.594ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.329 ns" { PWORD[4] REG10B:u5|DOUT[6]~46 REG10B:u5|DOUT[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.329 ns" { PWORD[4] PWORD[4]~out0 REG10B:u5|DOUT[6]~46 REG10B:u5|DOUT[7] } { 0.000ns 0.000ns 5.099ns 0.000ns } { 0.000ns 1.135ns 0.449ns 0.646ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.271 ns" { CLK REG10B:u5|DOUT[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.271 ns" { CLK CLK~out0 REG10B:u5|DOUT[7] } { 0.000ns 0.000ns 0.594ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK FOUT\[3\] sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|q_a\[3\] 6.786 ns memory " "Info: tco from clock \"CLK\" to destination pin \"FOUT\[3\]\" through memory \"sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|q_a\[3\]\" is 6.786 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.260 ns + Longest memory " "Info: + Longest clock path from clock \"CLK\" to source memory is 2.260 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns CLK 1 CLK PIN_29 102 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 102; CLK Node = 'CLK'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "DDS_VHDL.vhd" "" { Text "C:/testlog/DDS_VHDL.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.585 ns) + CELL(0.545 ns) 2.260 ns sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|q_a\[3\] 2 MEM M4K_X17_Y10 1 " "Info: 2: + IC(0.585 ns) + CELL(0.545 ns) = 2.260 ns; Loc. = M4K_X17_Y10; Fanout = 1; MEM Node = 'sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|q_a\[3\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.130 ns" { CLK sin_rom:u3|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[3] } "NODE_NAME" } } { "db/altsyncram_u631.tdf" "" { Text "C:/testlog/db/altsyncram_u631.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.675 ns ( 74.12 % ) " "Info: Total cell delay = 1.675 ns ( 74.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.585 ns ( 25.88 % ) " "Info: Total interconnect delay = 0.585 ns ( 25.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.260 ns" { CLK sin_rom:u3|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.260 ns" { CLK CLK~out0 sin_rom:u3|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[3] } { 0.000ns 0.000ns 0.585ns } { 0.000ns 1.130ns 0.545ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "db/altsyncram_u631.tdf" "" { Text "C:/testlog/db/altsyncram_u631.tdf" 40 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.026 ns + Longest memory pin " "Info: + Longest memory to pin delay is 4.026 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 0.080 ns sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|q_a\[3\] 1 MEM M4K_X17_Y10 1 " "Info: 1: + IC(0.000 ns) + CELL(0.080 ns) = 0.080 ns; Loc. = M4K_X17_Y10; Fanout = 1; MEM Node = 'sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|q_a\[3\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[3] } "NODE_NAME" } } { "db/altsyncram_u631.tdf" "" { Text "C:/testlog/db/altsyncram_u631.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.312 ns) + CELL(1.634 ns) 4.026 ns FOUT\[3\] 2 PIN PIN_143 0 " "Info: 2: + IC(2.312 ns) + CELL(1.634 ns) = 4.026 ns; Loc. = PIN_143; Fanout = 0; PIN Node = 'FOUT\[3\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.946 ns" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[3] FOUT[3] } "NODE_NAME" } } { "DDS_VHDL.vhd" "" { Text "C:/testlog/DDS_VHDL.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.714 ns ( 42.57 % ) " "Info: Total cell delay = 1.714 ns ( 42.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.312 ns ( 57.43 % ) " "Info: Total interconnect delay = 2.312 ns ( 57.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.026 ns" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[3] FOUT[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.026 ns" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[3] FOUT[3] } { 0.000ns 2.312ns } { 0.080ns 1.634ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.260 ns" { CLK sin_rom:u3|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.260 ns" { CLK CLK~out0 sin_rom:u3|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[3] } { 0.000ns 0.000ns 0.585ns } { 0.000ns 1.130ns 0.545ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.026 ns" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[3] FOUT[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.026 ns" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[3] FOUT[3] } { 0.000ns 2.312ns } { 0.080ns 1.634ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "REG32B:u2\|DOUT\[23\] FWORD\[3\] CLK -0.871 ns register " "Info: th for register \"REG32B:u2\|DOUT\[23\]\" (data pin = \"FWORD\[3\]\", clock pin = \"CLK\") is -0.871 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.271 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 2.271 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns CLK 1 CLK PIN_29 102 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 102; CLK Node = 'CLK'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "DDS_VHDL.vhd" "" { Text "C:/testlog/DDS_VHDL.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.594 ns) + CELL(0.547 ns) 2.271 ns REG32B:u2\|DOUT\[23\] 2 REG LC_X16_Y15_N7 7 " "Info: 2: + IC(0.594 ns) + CELL(0.547 ns) = 2.271 ns; Loc. = LC_X16_Y15_N7; Fanout = 7; REG Node = 'REG32B:u2\|DOUT\[23\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.141 ns" { CLK REG32B:u2|DOUT[23] } "NODE_NAME" } } { "REG32B.vhd" "" { Text "C:/testlog/REG32B.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 73.84 % ) " "Info: Total cell delay = 1.677 ns ( 73.84 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.594 ns ( 26.16 % ) " "Info: Total interconnect delay = 0.594 ns ( 26.16 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.271 ns" { CLK REG32B:u2|DOUT[23] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.271 ns" { CLK CLK~out0 REG32B:u2|DOUT[23] } { 0.000ns 0.000ns 0.594ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.012 ns + " "Info: + Micro hold delay of destination is 0.012 ns" {  } { { "REG32B.vhd" "" { Text "C:/testlog/REG32B.vhd" 12 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.154 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.154 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns FWORD\[3\] 1 PIN PIN_28 3 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_28; Fanout = 3; PIN Node = 'FWORD\[3\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FWORD[3] } "NODE_NAME" } } { "DDS_VHDL.vhd" "" { Text "C:/testlog/DDS_VHDL.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.557 ns) + CELL(0.467 ns) 3.154 ns REG32B:u2\|DOUT\[23\] 2 REG LC_X16_Y15_N7 7 " "Info: 2: + IC(1.557 ns) + CELL(0.467 ns) = 3.154 ns; Loc. = LC_X16_Y15_N7; Fanout = 7; REG Node = 'REG32B:u2\|DOUT\[23\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.024 ns" { FWORD[3] REG32B:u2|DOUT[23] } "NODE_NAME" } } { "REG32B.vhd" "" { Text "C:/testlog/REG32B.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.597 ns ( 50.63 % ) " "Info: Total cell delay = 1.597 ns ( 50.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.557 ns ( 49.37 % ) " "Info: Total interconnect delay = 1.557 ns ( 49.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.154 ns" { FWORD[3] REG32B:u2|DOUT[23] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.154 ns" { FWORD[3] FWORD[3]~out0 REG32B:u2|DOUT[23] } { 0.000ns 0.000ns 1.557ns } { 0.000ns 1.130ns 0.467ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.271 ns" { CLK REG32B:u2|DOUT[23] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.271 ns" { CLK CLK~out0 REG32B:u2|DOUT[23] } { 0.000ns 0.000ns 0.594ns } { 0.000ns 1.130ns 0.547ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.154 ns" { FWORD[3] REG32B:u2|DOUT[23] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.154 ns" { FWORD[3] FWORD[3]~out0 REG32B:u2|DOUT[23] } { 0.000ns 0.000ns 1.557ns } { 0.000ns 1.130ns 0.467ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}