prev_cmp_dds_vhdl.tan.qmsg

dds移相信号发生器 VHDL语言代码

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock memory altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|ram_block1a0~porta_address_reg0 memory altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|q_a\[0\] 256.02 MHz 3.906 ns Internal " "Info: Clock \"clock\" has Internal fmax of 256.02 MHz between source memory \"altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|ram_block1a0~porta_address_reg0\" and destination memory \"altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|q_a\[0\]\" (period= 3.906 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.323 ns + Longest memory memory " "Info: + Longest memory to memory delay is 3.323 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|ram_block1a0~porta_address_reg0 1 MEM M4K_X17_Y16 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X17_Y16; Fanout = 4; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|ram_block1a0~porta_address_reg0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { altsyncram:altsyncram_component|altsyncram_u631:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_u631.tdf" "" { Text "C:/testlog/db/altsyncram_u631.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.323 ns) 3.323 ns altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|q_a\[0\] 2 MEM M4K_X17_Y16 1 " "Info: 2: + IC(0.000 ns) + CELL(3.323 ns) = 3.323 ns; Loc. = M4K_X17_Y16; Fanout = 1; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|q_a\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.323 ns" { altsyncram:altsyncram_component|altsyncram_u631:auto_generated|ram_block1a0~porta_address_reg0 altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[0] } "NODE_NAME" } } { "db/altsyncram_u631.tdf" "" { Text "C:/testlog/db/altsyncram_u631.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.323 ns ( 100.00 % ) " "Info: Total cell delay = 3.323 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.323 ns" { altsyncram:altsyncram_component|altsyncram_u631:auto_generated|ram_block1a0~porta_address_reg0 altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.323 ns" { altsyncram:altsyncram_component|altsyncram_u631:auto_generated|ram_block1a0~porta_address_reg0 altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[0] } { 0.000ns 0.000ns } { 0.000ns 3.323ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.011 ns - Smallest " "Info: - Smallest clock skew is -0.011 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.275 ns + Shortest memory " "Info: + Shortest clock path from clock \"clock\" to destination memory is 2.275 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clock 1 CLK PIN_29 40 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 40; CLK Node = 'clock'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "sin_rom.vhd" "" { Text "C:/testlog/sin_rom.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(0.545 ns) 2.275 ns altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|q_a\[0\] 2 MEM M4K_X17_Y16 1 " "Info: 2: + IC(0.600 ns) + CELL(0.545 ns) = 2.275 ns; Loc. = M4K_X17_Y16; Fanout = 1; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|q_a\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.145 ns" { clock altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[0] } "NODE_NAME" } } { "db/altsyncram_u631.tdf" "" { Text "C:/testlog/db/altsyncram_u631.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.675 ns ( 73.63 % ) " "Info: Total cell delay = 1.675 ns ( 73.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.600 ns ( 26.37 % ) " "Info: Total interconnect delay = 0.600 ns ( 26.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.275 ns" { clock altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.275 ns" { clock clock~out0 altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[0] } { 0.000ns 0.000ns 0.600ns } { 0.000ns 1.130ns 0.545ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.286 ns - Longest memory " "Info: - Longest clock path from clock \"clock\" to source memory is 2.286 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clock 1 CLK PIN_29 40 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 40; CLK Node = 'clock'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "sin_rom.vhd" "" { Text "C:/testlog/sin_rom.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(0.556 ns) 2.286 ns altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|ram_block1a0~porta_address_reg0 2 MEM M4K_X17_Y16 4 " "Info: 2: + IC(0.600 ns) + CELL(0.556 ns) = 2.286 ns; Loc. = M4K_X17_Y16; Fanout = 4; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|ram_block1a0~porta_address_reg0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.156 ns" { clock altsyncram:altsyncram_component|altsyncram_u631:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_u631.tdf" "" { Text "C:/testlog/db/altsyncram_u631.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.686 ns ( 73.75 % ) " "Info: Total cell delay = 1.686 ns ( 73.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.600 ns ( 26.25 % ) " "Info: Total interconnect delay = 0.600 ns ( 26.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.286 ns" { clock altsyncram:altsyncram_component|altsyncram_u631:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.286 ns" { clock clock~out0 altsyncram:altsyncram_component|altsyncram_u631:auto_generated|ram_block1a0~porta_address_reg0 } { 0.000ns 0.000ns 0.600ns } { 0.000ns 1.130ns 0.556ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.275 ns" { clock altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.275 ns" { clock clock~out0 altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[0] } { 0.000ns 0.000ns 0.600ns } { 0.000ns 1.130ns 0.545ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.286 ns" { clock altsyncram:altsyncram_component|altsyncram_u631:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.286 ns" { clock clock~out0 altsyncram:altsyncram_component|altsyncram_u631:auto_generated|ram_block1a0~porta_address_reg0 } { 0.000ns 0.000ns 0.600ns } { 0.000ns 1.130ns 0.556ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "db/altsyncram_u631.tdf" "" { Text "C:/testlog/db/altsyncram_u631.tdf" 43 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.072 ns + " "Info: + Micro setup delay of destination is 0.072 ns" {  } { { "db/altsyncram_u631.tdf" "" { Text "C:/testlog/db/altsyncram_u631.tdf" 40 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.323 ns" { altsyncram:altsyncram_component|altsyncram_u631:auto_generated|ram_block1a0~porta_address_reg0 altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.323 ns" { altsyncram:altsyncram_component|altsyncram_u631:auto_generated|ram_block1a0~porta_address_reg0 altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[0] } { 0.000ns 0.000ns } { 0.000ns 3.323ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.275 ns" { clock altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.275 ns" { clock clock~out0 altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[0] } { 0.000ns 0.000ns 0.600ns } { 0.000ns 1.130ns 0.545ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.286 ns" { clock altsyncram:altsyncram_component|altsyncram_u631:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.286 ns" { clock clock~out0 altsyncram:altsyncram_component|altsyncram_u631:auto_generated|ram_block1a0~porta_address_reg0 } { 0.000ns 0.000ns 0.600ns } { 0.000ns 1.130ns 0.556ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|ram_block1a4~porta_address_reg9 address\[9\] clock 5.536 ns memory " "Info: tsu for memory \"altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|ram_block1a4~porta_address_reg9\" (data pin = \"address\[9\]\", clock pin = \"clock\") is 5.536 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.750 ns + Longest pin memory " "Info: + Longest pin to memory delay is 7.750 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns address\[9\] 1 PIN PIN_87 3 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_87; Fanout = 3; PIN Node = 'address\[9\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { address[9] } "NODE_NAME" } } { "sin_rom.vhd" "" { Text "C:/testlog/sin_rom.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.320 ns) + CELL(0.295 ns) 7.750 ns altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|ram_block1a4~porta_address_reg9 2 MEM M4K_X17_Y17 4 " "Info: 2: + IC(6.320 ns) + CELL(0.295 ns) = 7.750 ns; Loc. = M4K_X17_Y17; Fanout = 4; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|ram_block1a4~porta_address_reg9'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.615 ns" { address[9] altsyncram:altsyncram_component|altsyncram_u631:auto_generated|ram_block1a4~porta_address_reg9 } "NODE_NAME" } } { "db/altsyncram_u631.tdf" "" { Text "C:/testlog/db/altsyncram_u631.tdf" 123 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.430 ns ( 18.45 % ) " "Info: Total cell delay = 1.430 ns ( 18.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.320 ns ( 81.55 % ) " "Info: Total interconnect delay = 6.320 ns ( 81.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.750 ns" { address[9] altsyncram:altsyncram_component|altsyncram_u631:auto_generated|ram_block1a4~porta_address_reg9 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.750 ns" { address[9] address[9]~out0 altsyncram:altsyncram_component|altsyncram_u631:auto_generated|ram_block1a4~porta_address_reg9 } { 0.000ns 0.000ns 6.320ns } { 0.000ns 1.135ns 0.295ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.072 ns + " "Info: + Micro setup delay of destination is 0.072 ns" {  } { { "db/altsyncram_u631.tdf" "" { Text "C:/testlog/db/altsyncram_u631.tdf" 123 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.286 ns - Shortest memory " "Info: - Shortest clock path from clock \"clock\" to destination memory is 2.286 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clock 1 CLK PIN_29 40 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 40; CLK Node = 'clock'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "sin_rom.vhd" "" { Text "C:/testlog/sin_rom.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(0.556 ns) 2.286 ns altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|ram_block1a4~porta_address_reg9 2 MEM M4K_X17_Y17 4 " "Info: 2: + IC(0.600 ns) + CELL(0.556 ns) = 2.286 ns; Loc. = M4K_X17_Y17; Fanout = 4; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|ram_block1a4~porta_address_reg9'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.156 ns" { clock altsyncram:altsyncram_component|altsyncram_u631:auto_generated|ram_block1a4~porta_address_reg9 } "NODE_NAME" } } { "db/altsyncram_u631.tdf" "" { Text "C:/testlog/db/altsyncram_u631.tdf" 123 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.686 ns ( 73.75 % ) " "Info: Total cell delay = 1.686 ns ( 73.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.600 ns ( 26.25 % ) " "Info: Total interconnect delay = 0.600 ns ( 26.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.286 ns" { clock altsyncram:altsyncram_component|altsyncram_u631:auto_generated|ram_block1a4~porta_address_reg9 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.286 ns" { clock clock~out0 altsyncram:altsyncram_component|altsyncram_u631:auto_generated|ram_block1a4~porta_address_reg9 } { 0.000ns 0.000ns 0.600ns } { 0.000ns 1.130ns 0.556ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.750 ns" { address[9] altsyncram:altsyncram_component|altsyncram_u631:auto_generated|ram_block1a4~porta_address_reg9 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.750 ns" { address[9] address[9]~out0 altsyncram:altsyncram_component|altsyncram_u631:auto_generated|ram_block1a4~porta_address_reg9 } { 0.000ns 0.000ns 6.320ns } { 0.000ns 1.135ns 0.295ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.286 ns" { clock altsyncram:altsyncram_component|altsyncram_u631:auto_generated|ram_block1a4~porta_address_reg9 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.286 ns" { clock clock~out0 altsyncram:altsyncram_component|altsyncram_u631:auto_generated|ram_block1a4~porta_address_reg9 } { 0.000ns 0.000ns 0.600ns } { 0.000ns 1.130ns 0.556ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock q\[4\] altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|q_a\[4\] 6.848 ns memory " "Info: tco from clock \"clock\" to destination pin \"q\[4\]\" through memory \"altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|q_a\[4\]\" is 6.848 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.275 ns + Longest memory " "Info: + Longest clock path from clock \"clock\" to source memory is 2.275 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clock 1 CLK PIN_29 40 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 40; CLK Node = 'clock'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "sin_rom.vhd" "" { Text "C:/testlog/sin_rom.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(0.545 ns) 2.275 ns altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|q_a\[4\] 2 MEM M4K_X17_Y17 1 " "Info: 2: + IC(0.600 ns) + CELL(0.545 ns) = 2.275 ns; Loc. = M4K_X17_Y17; Fanout = 1; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|q_a\[4\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.145 ns" { clock altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[4] } "NODE_NAME" } } { "db/altsyncram_u631.tdf" "" { Text "C:/testlog/db/altsyncram_u631.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.675 ns ( 73.63 % ) " "Info: Total cell delay = 1.675 ns ( 73.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.600 ns ( 26.37 % ) " "Info: Total interconnect delay = 0.600 ns ( 26.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.275 ns" { clock altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[4] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.275 ns" { clock clock~out0 altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[4] } { 0.000ns 0.000ns 0.600ns } { 0.000ns 1.130ns 0.545ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "db/altsyncram_u631.tdf" "" { Text "C:/testlog/db/altsyncram_u631.tdf" 40 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.073 ns + Longest memory pin " "Info: + Longest memory to pin delay is 4.073 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 0.080 ns altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|q_a\[4\] 1 MEM M4K_X17_Y17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.080 ns) = 0.080 ns; Loc. = M4K_X17_Y17; Fanout = 1; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|q_a\[4\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[4] } "NODE_NAME" } } { "db/altsyncram_u631.tdf" "" { Text "C:/testlog/db/altsyncram_u631.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.359 ns) + CELL(1.634 ns) 4.073 ns q\[4\] 2 PIN PIN_7 0 " "Info: 2: + IC(2.359 ns) + CELL(1.634 ns) = 4.073 ns; Loc. = PIN_7; Fanout = 0; PIN Node = 'q\[4\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.993 ns" { altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[4] q[4] } "NODE_NAME" } } { "sin_rom.vhd" "" { Text "C:/testlog/sin_rom.vhd" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.714 ns ( 42.08 % ) " "Info: Total cell delay = 1.714 ns ( 42.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.359 ns ( 57.92 % ) " "Info: Total interconnect delay = 2.359 ns ( 57.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.073 ns" { altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[4] q[4] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.073 ns" { altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[4] q[4] } { 0.000ns 2.359ns } { 0.080ns 1.634ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.275 ns" { clock altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[4] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.275 ns" { clock clock~out0 altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[4] } { 0.000ns 0.000ns 0.600ns } { 0.000ns 1.130ns 0.545ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.073 ns" { altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[4] q[4] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.073 ns" { altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[4] q[4] } { 0.000ns 2.359ns } { 0.080ns 1.634ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|ram_block1a4~porta_address_reg4 address\[4\] clock -3.137 ns memory " "Info: th for memory \"altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|ram_block1a4~porta_address_reg4\" (data pin = \"address\[4\]\", clock pin = \"clock\") is -3.137 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.286 ns + Longest memory " "Info: + Longest clock path from clock \"clock\" to destination memory is 2.286 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clock 1 CLK PIN_29 40 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 40; CLK Node = 'clock'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "sin_rom.vhd" "" { Text "C:/testlog/sin_rom.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(0.556 ns) 2.286 ns altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|ram_block1a4~porta_address_reg4 2 MEM M4K_X17_Y17 4 " "Info: 2: + IC(0.600 ns) + CELL(0.556 ns) = 2.286 ns; Loc. = M4K_X17_Y17; Fanout = 4; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|ram_block1a4~porta_address_reg4'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.156 ns" { clock altsyncram:altsyncram_component|altsyncram_u631:auto_generated|ram_block1a4~porta_address_reg4 } "NODE_NAME" } } { "db/altsyncram_u631.tdf" "" { Text "C:/testlog/db/altsyncram_u631.tdf" 123 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.686 ns ( 73.75 % ) " "Info: Total cell delay = 1.686 ns ( 73.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.600 ns ( 26.25 % ) " "Info: Total interconnect delay = 0.600 ns ( 26.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.286 ns" { clock altsyncram:altsyncram_component|altsyncram_u631:auto_generated|ram_block1a4~porta_address_reg4 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.286 ns" { clock clock~out0 altsyncram:altsyncram_component|altsyncram_u631:auto_generated|ram_block1a4~porta_address_reg4 } { 0.000ns 0.000ns 0.600ns } { 0.000ns 1.130ns 0.556ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.043 ns + " "Info: + Micro hold delay of destination is 0.043 ns" {  } { { "db/altsyncram_u631.tdf" "" { Text "C:/testlog/db/altsyncram_u631.tdf" 123 2 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.466 ns - Shortest pin memory " "Info: - Shortest pin to memory delay is 5.466 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns address\[4\] 1 PIN PIN_208 3 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_208; Fanout = 3; PIN Node = 'address\[4\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { address[4] } "NODE_NAME" } } { "sin_rom.vhd" "" { Text "C:/testlog/sin_rom.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.036 ns) + CELL(0.295 ns) 5.466 ns altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|ram_block1a4~porta_address_reg4 2 MEM M4K_X17_Y17 4 " "Info: 2: + IC(4.036 ns) + CELL(0.295 ns) = 5.466 ns; Loc. = M4K_X17_Y17; Fanout = 4; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|ram_block1a4~porta_address_reg4'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.331 ns" { address[4] altsyncram:altsyncram_component|altsyncram_u631:auto_generated|ram_block1a4~porta_address_reg4 } "NODE_NAME" } } { "db/altsyncram_u631.tdf" "" { Text "C:/testlog/db/altsyncram_u631.tdf" 123 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.430 ns ( 26.16 % ) " "Info: Total cell delay = 1.430 ns ( 26.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.036 ns ( 73.84 % ) " "Info: Total interconnect delay = 4.036 ns ( 73.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.466 ns" { address[4] altsyncram:altsyncram_component|altsyncram_u631:auto_generated|ram_block1a4~porta_address_reg4 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.466 ns" { address[4] address[4]~out0 altsyncram:altsyncram_component|altsyncram_u631:auto_generated|ram_block1a4~porta_address_reg4 } { 0.000ns 0.000ns 4.036ns } { 0.000ns 1.135ns 0.295ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.286 ns" { clock altsyncram:altsyncram_component|altsyncram_u631:auto_generated|ram_block1a4~porta_address_reg4 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.286 ns" { clock clock~out0 altsyncram:altsyncram_component|altsyncram_u631:auto_generated|ram_block1a4~porta_address_reg4 } { 0.000ns 0.000ns 0.600ns } { 0.000ns 1.130ns 0.556ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.466 ns" { address[4] altsyncram:altsyncram_component|altsyncram_u631:auto_generated|ram_block1a4~porta_address_reg4 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.466 ns" { address[4] address[4]~out0 altsyncram:altsyncram_component|altsyncram_u631:auto_generated|ram_block1a4~porta_address_reg4 } { 0.000ns 0.000ns 4.036ns } { 0.000ns 1.135ns 0.295ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}