prev_cmp_dds_vhdl.qmsg

dds移相信号发生器 VHDL语言代码

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_u631.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_u631.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_u631 " "Info: Found entity 1: altsyncram_u631" {  } { { "db/altsyncram_u631.tdf" "" { Text "C:/testlog/db/altsyncram_u631.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_u631 sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_u631:auto_generated " "Info: Elaborating entity \"altsyncram_u631\" for hierarchy \"sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/71/quartus/libraries/megafunctions/altsyncram.tdf" 918 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ADDER10B ADDER10B:u4 " "Info: Elaborating entity \"ADDER10B\" for hierarchy \"ADDER10B:u4\"" {  } { { "DDS_VHDL.vhd" "u4" { Text "C:/testlog/DDS_VHDL.vhd" 50 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "REG10B REG10B:u5 " "Info: Elaborating entity \"REG10B\" for hierarchy \"REG10B:u5\"" {  } { { "DDS_VHDL.vhd" "u5" { Text "C:/testlog/DDS_VHDL.vhd" 51 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "REG32B:u2\|DOUT\[18\] REG32B:u2\|DOUT\[0\] " "Info: Duplicate register \"REG32B:u2\|DOUT\[18\]\" merged to single register \"REG32B:u2\|DOUT\[0\]\"" {  } { { "REG32B.vhd" "" { Text "C:/testlog/REG32B.vhd" 12 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "REG32B:u2\|DOUT\[10\] REG32B:u2\|DOUT\[0\] " "Info: Duplicate register \"REG32B:u2\|DOUT\[10\]\" merged to single register \"REG32B:u2\|DOUT\[0\]\"" {  } { { "REG32B.vhd" "" { Text "C:/testlog/REG32B.vhd" 12 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "REG32B:u2\|DOUT\[4\] REG32B:u2\|DOUT\[0\] " "Info: Duplicate register \"REG32B:u2\|DOUT\[4\]\" merged to single register \"REG32B:u2\|DOUT\[0\]\"" {  } { { "REG32B.vhd" "" { Text "C:/testlog/REG32B.vhd" 12 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "REG32B:u2\|DOUT\[16\] REG32B:u2\|DOUT\[0\] " "Info: Duplicate register \"REG32B:u2\|DOUT\[16\]\" merged to single register \"REG32B:u2\|DOUT\[0\]\"" {  } { { "REG32B.vhd" "" { Text "C:/testlog/REG32B.vhd" 12 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "REG32B:u2\|DOUT\[12\] REG32B:u2\|DOUT\[0\] " "Info: Duplicate register \"REG32B:u2\|DOUT\[12\]\" merged to single register \"REG32B:u2\|DOUT\[0\]\"" {  } { { "REG32B.vhd" "" { Text "C:/testlog/REG32B.vhd" 12 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "REG32B:u2\|DOUT\[8\] REG32B:u2\|DOUT\[0\] " "Info: Duplicate register \"REG32B:u2\|DOUT\[8\]\" merged to single register \"REG32B:u2\|DOUT\[0\]\"" {  } { { "REG32B.vhd" "" { Text "C:/testlog/REG32B.vhd" 12 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "REG32B:u2\|DOUT\[19\] REG32B:u2\|DOUT\[0\] " "Info: Duplicate register \"REG32B:u2\|DOUT\[19\]\" merged to single register \"REG32B:u2\|DOUT\[0\]\"" {  } { { "REG32B.vhd" "" { Text "C:/testlog/REG32B.vhd" 12 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "REG32B:u2\|DOUT\[1\] REG32B:u2\|DOUT\[0\] " "Info: Duplicate register \"REG32B:u2\|DOUT\[1\]\" merged to single register \"REG32B:u2\|DOUT\[0\]\"" {  } { { "REG32B.vhd" "" { Text "C:/testlog/REG32B.vhd" 12 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "REG32B:u2\|DOUT\[11\] REG32B:u2\|DOUT\[0\] " "Info: Duplicate register \"REG32B:u2\|DOUT\[11\]\" merged to single register \"REG32B:u2\|DOUT\[0\]\"" {  } { { "REG32B.vhd" "" { Text "C:/testlog/REG32B.vhd" 12 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "REG32B:u2\|DOUT\[5\] REG32B:u2\|DOUT\[0\] " "Info: Duplicate register \"REG32B:u2\|DOUT\[5\]\" merged to single register \"REG32B:u2\|DOUT\[0\]\"" {  } { { "REG32B.vhd" "" { Text "C:/testlog/REG32B.vhd" 12 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "REG32B:u2\|DOUT\[15\] REG32B:u2\|DOUT\[0\] " "Info: Duplicate register \"REG32B:u2\|DOUT\[15\]\" merged to single register \"REG32B:u2\|DOUT\[0\]\"" {  } { { "REG32B.vhd" "" { Text "C:/testlog/REG32B.vhd" 12 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "REG32B:u2\|DOUT\[13\] REG32B:u2\|DOUT\[0\] " "Info: Duplicate register \"REG32B:u2\|DOUT\[13\]\" merged to single register \"REG32B:u2\|DOUT\[0\]\"" {  } { { "REG32B.vhd" "" { Text "C:/testlog/REG32B.vhd" 12 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "REG32B:u2\|DOUT\[7\] REG32B:u2\|DOUT\[0\] " "Info: Duplicate register \"REG32B:u2\|DOUT\[7\]\" merged to single register \"REG32B:u2\|DOUT\[0\]\"" {  } { { "REG32B.vhd" "" { Text "C:/testlog/REG32B.vhd" 12 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "REG32B:u2\|DOUT\[17\] REG32B:u2\|DOUT\[0\] " "Info: Duplicate register \"REG32B:u2\|DOUT\[17\]\" merged to single register \"REG32B:u2\|DOUT\[0\]\"" {  } { { "REG32B.vhd" "" { Text "C:/testlog/REG32B.vhd" 12 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "REG32B:u2\|DOUT\[3\] REG32B:u2\|DOUT\[0\] " "Info: Duplicate register \"REG32B:u2\|DOUT\[3\]\" merged to single register \"REG32B:u2\|DOUT\[0\]\"" {  } { { "REG32B.vhd" "" { Text "C:/testlog/REG32B.vhd" 12 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "REG32B:u2\|DOUT\[9\] REG32B:u2\|DOUT\[0\] " "Info: Duplicate register \"REG32B:u2\|DOUT\[9\]\" merged to single register \"REG32B:u2\|DOUT\[0\]\"" {  } { { "REG32B.vhd" "" { Text "C:/testlog/REG32B.vhd" 12 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "REG32B:u2\|DOUT\[2\] REG32B:u2\|DOUT\[0\] " "Info: Duplicate register \"REG32B:u2\|DOUT\[2\]\" merged to single register \"REG32B:u2\|DOUT\[0\]\"" {  } { { "REG32B.vhd" "" { Text "C:/testlog/REG32B.vhd" 12 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "REG32B:u2\|DOUT\[6\] REG32B:u2\|DOUT\[0\] " "Info: Duplicate register \"REG32B:u2\|DOUT\[6\]\" merged to single register \"REG32B:u2\|DOUT\[0\]\"" {  } { { "REG32B.vhd" "" { Text "C:/testlog/REG32B.vhd" 12 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "REG32B:u2\|DOUT\[14\] REG32B:u2\|DOUT\[0\] " "Info: Duplicate register \"REG32B:u2\|DOUT\[14\]\" merged to single register \"REG32B:u2\|DOUT\[0\]\"" {  } { { "REG32B.vhd" "" { Text "C:/testlog/REG32B.vhd" 12 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "REG32B:u2\|DOUT\[0\] data_in GND " "Warning: Reduced register \"REG32B:u2\|DOUT\[0\]\" with stuck data_in port to stuck value GND" {  } { { "REG32B.vhd" "" { Text "C:/testlog/REG32B.vhd" 12 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "79 " "Info: Implemented 79 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "17 " "Info: Implemented 17 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "20 " "Info: Implemented 20 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "22 " "Info: Implemented 22 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0} { "Info" "ICUT_CUT_TM_RAMS" "20 " "Info: Implemented 20 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "150 " "Info: Allocated 150 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 10 19:36:10 2008 " "Info: Processing ended: Sun Aug 10 19:36:10 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 10 19:36:12 2008 " "Info: Processing started: Sun Aug 10 19:36:12 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off DDS_VHDL -c DDS_VHDL " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off DDS_VHDL -c DDS_VHDL" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "DDS_VHDL EP1C6Q240C6 " "Info: Selected device EP1C6Q240C6 for design \"DDS_VHDL\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0}
{ "Info" "IFITCC_FITCC_QID_PARTITION_BACK_ANNOTATION_TOP" "1 0 " "Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use" { { "Info" "IFITCC_FITCC_QID_PARTITION_BACK_ANNOTATION_NONE_OVERRIDE" "79 Top " "Info: Previous placement does not exist for 79 of 79 atoms in partition Top" {  } {  } 0 0 "Previous placement does not exist for %1!d! of %1!d! atoms in partition %2!s!" 0 0 "" 0}  } {  } 0 0 "The Fitter has identified %1!d! logical partitions of which %2!d! have a previous placement to use" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C12Q240C6 " "Info: Device EP1C12Q240C6 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "2 " "Info: Fitter converted 2 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 24 " "Info: Pin ~nCSO~ is reserved at location 24" {  } {  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 37 " "Info: Pin ~ASDO~ is reserved at location 37" {  } {  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0}  } {  } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0}