📄 darr80_func.c
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/******************************************************************************
*
* Purpose: Max II configuration strings and application settings
*
* Creator: Rob Lansbergen
*
* Version: $Revision: 86 $
*
* File Name: $Workfile: DARR80_Func.c $
*
* Author: Rob Lansbergen
*
* Check in: $Author: Chong.cheeleong $
*
* The information is provided 揳s is?without any express or implied warranty
* of any kind, * including warranties of merchantability, noninfringement of
* intellectual property, or fitness for any particular purpose. In no event sha
* Wireless Sound Solutions and/or its affiliate companies, or its suppliers be
* liable for any damages whatsoever arising out of the use of or inability to
* use the information or the materials. Wireless Sound Solutions, its affiliate
* companies, and its suppliers further do not warrant the accuracy or
* completeness of information, text, graphics, or other items contained within
* materials. Wireless Sound Solutions, Inc., may make changes to materials, or
* the products described within, at any time, without notice.
* ?007 Wireless Sound Solutions. All rights reserved. Wireless Sound Solutions
* STS and STS-wireless are trademarks of Wireless Sound Solutions.
********************************************************************************/
#include <stdio.h>
#include "pgmspace.h"
#include "defines.h"
/* Going from 2 applic to 6 application cost 1840 Bytes */
/* 1 application costs 460 Bytes */
/* 6 applications loaded, 297 Bytes free */
/* 2 applications loaded, 297+1840=2137 Bytes free, 26 jun 2006 */
/* Remove Unused applications */
#if defined( CF1 ) || defined ( CF3 ) /* only for 22MHz clock configurations */
#ifdef Stereo_1_NAck_CF1
#include "DARR80_ApplCfg_1 Stereo NAck_CF1.h" /* 0 */
#endif
#ifdef Stereo_2_NAck_CF1
#include "DARR80_ApplCfg_2 Stereo NAck_CF1.h" /* 1 */
#endif
#ifdef Stereo_3_NAck_CF1
#include "DARR80_ApplCfg_3 Stereo NAck_CF1.h" /* 2 */
#endif
#ifdef Stereo_4_NAck_CF1
#include "DARR80_ApplCfg_4 Stereo NAck_CF1.h" /* 3 */
#endif
#ifdef HeadSet_1
#include "DARR80_ApplCfg_1 HeadSet (Stereo plus Voice Up)_CF1.h" /* 4 */
#endif
#ifdef HeadSet_2
#include "DARR80_ApplCfg_2 HeadSet (2 Stereo Plus 2 Voice Up)_CF1.h" /* 5 */
#endif
#endif
#if defined( CF2 ) || defined ( CF4 ) /* only for 24.576MHz clock configurations */
#ifdef Stereo_1_NAck_CF1
#include "DARR80_ApplCfg_1 Stereo NAck_CF2.h" /* 0 */
#endif
#ifdef Stereo_2_NAck_CF1
#include "DARR80_ApplCfg_2 Stereo NAck_CF2.h" /* 1 */
#endif
#ifdef Stereo_3_NAck_CF1
#include "DARR80_ApplCfg_3 Stereo NAck_CF2.h" /* 2 */
#endif
#ifdef Stereo_4_NAck_CF1
#include "DARR80_ApplCfg_4 Stereo NAck_CF2.h" /* 3 */
#endif
#ifdef HeadSet_1
#include "DARR80_ApplCfg_1 HeadSet (Stereo plus Voice Up)_CF2.h" /* 4 */
#endif
#ifdef HeadSet_2
#include "DARR80_ApplCfg_2 HeadSet (2 Stereo Plus 2 Voice Up)_CF2.h" /* 5 */
#endif
#endif
/* Local Function Definition */
unsigned char Write_Config_Strings(void);
unsigned char Audio_Status = AUDIO;
unsigned char Snooze_Delay;
unsigned char Snooze_Delay_Timeout = 100; /* 10 seconds */
//unsigned char Snooze_Delay_Timeout = 200;
unsigned char Snooze_Delay_Awake_Timeout=2;
unsigned char Sleep_threshold = 30;
unsigned char Sleep_Timer;
unsigned char Init_DARR(void);
/* external Function Definition */
extern unsigned char Config_MAX2834(void);
/******************************************************************************
*
* Function Name : Init_DARR
*
* Purpose : Main Entry Point
* This Function will init the the DARR module
*
* Arguments : none
*
* Return value : Error
*
******************************************************************************/
unsigned char Init_DARR(void)
{
unsigned char Error = 0;
unsigned char volume = 0;
RESET_DARR(0);
Wait_For_mSec(100); /* Need some time because RC on reset is big */
RESET_DARR(1);
Wait_For_mSec(50);
InSync_Detected = 0;
Audio_Status = AUDIO;
Error = Write_Config_Strings();
/********************************************************************************/
/*** All Registers not writen up to here are using there default reset values ***/
/*** Application dependent settings will follow after this section ***/
/********************************************************************************/
Error += Config_System_Clock();
Error += Config_DARR80_General();
Error += Config_Modem();
volume = Get_Volume();
Restore_Volume(volume);
Write_GEC_ADDR( 0x01 + Connect_Bit);
return (Error);
}
/******************************************************************************
*
* Function Name : Write_Config_Strings
*
* Purpose : This Function will init the the DARR80
* Sequential loading of Configuration string and
* Application string.
*
* Arguments : None
*
* Use_Application:
* 0 = 1 Stereo NACK
* 1 = 2 Stereo NACK
* 2 = 3 Stereo NACK
* 3 = 4 Stereo NACK
* 4 = 1 Stereo ACK Headset
* 5 = 2 Stereo ACK Headset
* Use_Speaker_Enable_Bits: holds the information which audio
* stream should be enabled.
* 1 = left_A (pipe w)
* 2 = right_A (pipe x)
* 4 = left_B (pipe y)
* 8 = right_B (pipe z)
*
* Return value : 1 if there was a I2C error during configuration
* 0 when there was no Error
*
******************************************************************************/
unsigned char Write_Config_Strings(void)
{
unsigned char I2C_Error;
unsigned char ConfigDepth;
const unsigned char __flash *CFGS_Addr;
const unsigned char __flash *Appl_Sett_Addr;
unsigned char STAC_Value;
unsigned char PIAC_Value;
I2C_Error = 0;
/*******************************/
/*** Select Application Data ***/
/*******************************/
/* To save space choose an application and remove .h file */
#ifdef Stereo_1_NAck_CF1
if ((Use_ModuleMode == CU) && (Use_Application == 0)) {CFGS_Addr = MAXII_APPLIC_CFGS_CU_APPL_NO_0; ConfigDepth = CU_CONFIG_DEPTH_APPL_NO_0; Appl_Sett_Addr = MAXII_APPLIC_SETTINGS_CU_APPL_NO_0; }
if ((Use_ModuleMode == MU) && (Use_Application == 0)) {CFGS_Addr = MAXII_APPLIC_CFGS_MU_APPL_NO_0; ConfigDepth = MU_CONFIG_DEPTH_APPL_NO_0; Appl_Sett_Addr = MAXII_APPLIC_SETTINGS_MU_APPL_NO_0; }
#endif /*Stereo_1_NAck_CF1*/
#ifdef Stereo_2_NAck_CF1
if ((Use_ModuleMode == CU) && (Use_Application == 1)) {CFGS_Addr = MAXII_APPLIC_CFGS_CU_APPL_NO_1; ConfigDepth = CU_CONFIG_DEPTH_APPL_NO_1; Appl_Sett_Addr = MAXII_APPLIC_SETTINGS_CU_APPL_NO_1; }
if ((Use_ModuleMode == MU) && (Use_Application == 1)) {CFGS_Addr = MAXII_APPLIC_CFGS_MU_APPL_NO_1; ConfigDepth = MU_CONFIG_DEPTH_APPL_NO_1; Appl_Sett_Addr = MAXII_APPLIC_SETTINGS_MU_APPL_NO_1; }
#endif /*Stereo_2_NAck_CF1*/
#ifdef Stereo_3_NAck_CF1
if ((Use_ModuleMode == CU) && (Use_Application == 2)) {CFGS_Addr = MAXII_APPLIC_CFGS_CU_APPL_NO_2; ConfigDepth = CU_CONFIG_DEPTH_APPL_NO_2; Appl_Sett_Addr = MAXII_APPLIC_SETTINGS_CU_APPL_NO_2; }
if ((Use_ModuleMode == MU) && (Use_Application == 2)) {CFGS_Addr = MAXII_APPLIC_CFGS_MU_APPL_NO_2; ConfigDepth = MU_CONFIG_DEPTH_APPL_NO_2; Appl_Sett_Addr = MAXII_APPLIC_SETTINGS_MU_APPL_NO_2; }
#endif /*Stereo_3_NAck_CF1*/
#ifdef Stereo_4_NAck_CF1
if ((Use_ModuleMode == CU) && (Use_Application == 3)) {CFGS_Addr = MAXII_APPLIC_CFGS_CU_APPL_NO_3; ConfigDepth = CU_CONFIG_DEPTH_APPL_NO_3; Appl_Sett_Addr = MAXII_APPLIC_SETTINGS_CU_APPL_NO_3; }
if ((Use_ModuleMode == MU) && (Use_Application == 3)) {CFGS_Addr = MAXII_APPLIC_CFGS_MU_APPL_NO_3; ConfigDepth = MU_CONFIG_DEPTH_APPL_NO_3; Appl_Sett_Addr = MAXII_APPLIC_SETTINGS_MU_APPL_NO_3; }
#endif /*Stereo_4_NAck_CF1*/
#ifdef HeadSet_1
if ((Use_ModuleMode == CU) && (Use_Application == 4)) {CFGS_Addr = MAXII_APPLIC_CFGS_CU_APPL_NO_4; ConfigDepth = CU_CONFIG_DEPTH_APPL_NO_4; Appl_Sett_Addr = MAXII_APPLIC_SETTINGS_CU_APPL_NO_4; }
if ((Use_ModuleMode == MU) && (Use_Application == 4)) {CFGS_Addr = MAXII_APPLIC_CFGS_MU_APPL_NO_4; ConfigDepth = MU_CONFIG_DEPTH_APPL_NO_4; Appl_Sett_Addr = MAXII_APPLIC_SETTINGS_MU_APPL_NO_4; }
#endif /*HeadSet_1*/
#ifdef HeadSet_2
if ((Use_ModuleMode == CU) && (Use_Application == 5)) {CFGS_Addr = MAXII_APPLIC_CFGS_CU_APPL_NO_5; ConfigDepth = CU_CONFIG_DEPTH_APPL_NO_5; Appl_Sett_Addr = MAXII_APPLIC_SETTINGS_CU_APPL_NO_5; }
if ((Use_ModuleMode == MU) && (Use_Application == 5)) {CFGS_Addr = MAXII_APPLIC_CFGS_MU_APPL_NO_5; ConfigDepth = MU_CONFIG_DEPTH_APPL_NO_5; Appl_Sett_Addr = MAXII_APPLIC_SETTINGS_MU_APPL_NO_5; }
#endif /*HeadSet_2*/
// else
// {
// #ifdef DEBUG
// putstring("ERROR, No Config String Found\r");
// #endif
// /* switch back to 1 Stereo NACK application */
// Config_Byte1 = (0x20 | 0x00); /* MU | appl index = 0 */
// Use_ModuleMode = MU;
// Use_Application = 0;
// CFGS_Addr = MAXII_APPLIC_CFGS_MU_APPL_NO_0;
// ConfigDepth = MU_CONFIG_DEPTH_APPL_NO_0;
// Appl_Sett_Addr = MAXII_APPLIC_SETTINGS_MU_APPL_NO_0;
// #ifdef DEBUG
// putstring("Switched Back to Default Config MU 1 St NACK\r");
// #endif
// }
/***************************************/
/*** Copy Settings from FLASH to RAM ***/
/***************************************/
/****************************/
/*** Send Config String ***/
/****************************/
/* Write Config String to DARR with bit C of I2C slave addres set to one */
/* When Pin A0 and A1 are zero the I2C_SLAVE_ADDRESS should be 0x80 */
/* Set C Bit address to addres the upper 256 byte */
i2cSlaveAddress = I2C_SLAVE_ADDRESS | 0x02;
/* Write from address 0 to ConfigDepth with C bit set (is address 0x100) */
/* I2C_Write_Buf does a multiple I2C Write: */
/* I2C_Write_Buf(Start Address, Address to Write Buffer, amount of bytes, 1(read from flash)) */
I2C_Error += I2C_Write_Buf(COST_ADDR & 0xFF, (unsigned char *)CFGS_Addr, ConfigDepth, 1);
/**************************/
/*** Send Appl Settings ***/
/**************************/
/* Reset C Bit to address normal registers (low 256 byte) */
i2cSlaveAddress = I2C_SLAVE_ADDRESS;
/* Address APPL_ADDR to MAX_SETTINGS_DEPTH */
/* Depending on the application and default value not all value's need to be written */
/* It might be better to just write some registers to save code size */
/* I2C_Write_Buf does a multiple I2C Write: */
/* I2C_Write_Buf(Start Address, Address to Write Buffer, amount of bytes, 1(read from flash)) */
I2C_Error += I2C_Write_Buf(APPL_ADDR, (unsigned char *)Appl_Sett_Addr, MAX_SETTINGS_DEPTH, 1);
/***********************************/
/*** Configure Streams and Pipes ***/
/***********************************/
if (Use_ModuleMode == CU)
{
STAC_Value = Use_Speaker_Enable_Bits;
PIAC_Value = Use_Speaker_Enable_Bits << 4;
}
else
{
STAC_Value = Use_Speaker_Enable_Bits << 4;
PIAC_Value = Use_Speaker_Enable_Bits;
}
if (
(Use_Application == 4) ||
(Use_Application == 5)
)
{
/* for headset applications on pos 4 and 5 */
STAC_Value += PIAC_Value;
PIAC_Value = STAC_Value;
}
I2C_Error += I2C_Write_Byte(STAC_ADDR, STAC_Value);
I2C_Error += I2C_Write_Byte(PIAC_ADDR, PIAC_Value);
return (I2C_Error);
}
/******************************************************************************
*
* Function Name : Config_DARR80_General
*
* Purpose : General register initialisation for cold startup
* config by reset/powerup and warm startup reconfig by GUI
*
* Arguments : None
*
* Return value : I2C_Error
*
******************************************************************************/
unsigned char Config_DARR80_General(void)
{
unsigned char I2C_Error = 0;
unsigned char Reg_Value;
/***********************/
/*** GENERAL SECTION ***/
/***********************/
/* INTM: 20=(0x00) Interrut Mask */
/* freqsw int + insync and no_sync + Enable data */
I2C_Error += I2C_Write_Byte(INTM_ADDR, 0x40 + 0x30 + 0x0E);
/* No interrupts needed to get audio running, use value 0x00 disable all interupts */
/* PDDC: 22=(0x00) Power Down Duty Cycle */
if (Use_ModuleMode == MU) I2C_Error += I2C_Write_Byte(PDDC_ADDR, PDDC_SETTING); /* set fast Power down duty cycle mode */
else I2C_Error += I2C_Write_Byte(PDDC_ADDR, 0); /* reset fast Power down duty cycle mode */
/* MODE: 23=(0x00) Mode */
if (Use_ModuleMode == CU) I2C_Error += I2C_Write_Byte(MODE_ADDR, (0x00 + (Use_Application & 0x0F)));
else I2C_Error += I2C_Write_Byte(MODE_ADDR, (0x10 + (Use_Application & 0x0F)));
/*********************/
/*** Audio SECTION ***/
/*********************/
/* AICS: 31=(0x04) Audio Interface Control Status */
/******************************/
/*** 4 actual AICS settings ***/
/*** lsb nibble part only: ***/
/*** 1 0x1 L/RJ master ***/
/*** 2 0x6 I2S slave ***/
/*** 3 0x5 I2S master ***/
/*** 4 0x8 S/PDIF ***/
/******************************/
/*** bit3 bit2 bit1 bit0 ***/
/*** SPDIF_EN, I2S_LRJ, SL_BCK_EN, MA_BCK_EN ***/
/*** leave bit1 and bit0 settings unchanged !!! ***/
if (Use_SPDIF == 1)
{
Reg_Value = 0x08; /* Turn On S/PDIF enable, set bit3 */
}
else
{
#ifdef CODEC_CS5341
Reg_Value = 0x05; /* I2S interface Master (CODEC_CS5341 (ADC_input) is Slave) */
#endif /* CODEC_CS5341 */
#ifdef CODEC_CS5341_WM8728
/* for PCB_EVK_2CH */
Reg_Value = 0x05; /* bit2 = I2S, bit1 = master */
#endif /* CODEC_CS5341_WM8728 */
#ifdef AUDIO_CLK_OUT
Reg_Value += 0x80; /* bit7 = audio_clk_out_en */
/* Set bank5 slow 2 mA */
I2C_Error += I2C_Write_Byte(BK54_ADDR, 0x89);
#endif /* AUDIO_CLK_OUT */
#ifdef CODEC_CS4341
#ifdef PCB_PNP80_HEADSET //no use Allan
Reg_Value = 0x06; /* I2S interface slave (CODEC_CS4341 is master) */
#else
Reg_Value = 0x05; /* I2S interface master (CODEC_CS4341 is slave) */
#endif
#endif /* CODEC_CS4341 */
}
I2C_Error += I2C_Write_Byte(AICS_ADDR, Reg_Value);
/* AIC2: 32=(0x30) Audio Interface Control 2 */
I2C_Write_Byte(AIC2_ADDR, 0xF0);
/* TP2S: 36=(0xE4) TX Pipe 2 Stream */
#ifdef PCB_EVK_8CH
/* this Board has a mixed input */
/* Port A is Pipe Z */
/* Port B is Pipe X */
/* Port C is Pipe W */
/* Port D is pipe Y */
/* Also Left Right Input is Mixed Up */
I2C_Write_Byte(TP2S_ADDR, 0x36);
I2C_Write_Byte(AIC2_ADDR, 0x30);
#endif /* PCB_EVK_8CH */
#ifdef Target_CU
I2C_Write_Byte(AIC2_ADDR, 0x30);
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