p&e_icd.map

离合器控制

  _TB0DSR2 
SECTION: ".abs_section_557"
  _TB0DSR3 
SECTION: ".abs_section_558"
  _TB0DSR4 
SECTION: ".abs_section_559"
  _TB0DSR5 
SECTION: ".abs_section_55a"
  _TB0DSR6 
SECTION: ".abs_section_55b"
  _TB0DSR7 
SECTION: ".abs_section_55c"
  _TB0DLR 
SECTION: ".abs_section_55d"
  _TB0TBPR 
SECTION: ".abs_section_560"
  _TB1IDR0 
SECTION: ".abs_section_561"
  _TB1IDR1 
SECTION: ".abs_section_562"
  _TB1IDR2 
SECTION: ".abs_section_563"
  _TB1IDR3 
SECTION: ".abs_section_564"
  _TB1DSR0 
SECTION: ".abs_section_565"
  _TB1DSR1 
SECTION: ".abs_section_566"
  _TB1DSR2 
SECTION: ".abs_section_567"
  _TB1DSR3 
SECTION: ".abs_section_568"
  _TB1DSR4 
SECTION: ".abs_section_569"
  _TB1DSR5 
SECTION: ".abs_section_56a"
  _TB1DSR6 
SECTION: ".abs_section_56b"
  _TB1DSR7 
SECTION: ".abs_section_56c"
  _TB1DLR 
SECTION: ".abs_section_56d"
  _TB1TBPR 
SECTION: ".abs_section_570"
  _TB2IDR0 
SECTION: ".abs_section_571"
  _TB2IDR1 
SECTION: ".abs_section_572"
  _TB2IDR2 
SECTION: ".abs_section_573"
  _TB2IDR3 
SECTION: ".abs_section_574"
  _TB2DSR0 
SECTION: ".abs_section_575"
  _TB2DSR1 
SECTION: ".abs_section_576"
  _TB2DSR2 
SECTION: ".abs_section_577"
  _TB2DSR3 
SECTION: ".abs_section_578"
  _TB2DSR4 
SECTION: ".abs_section_579"
  _TB2DSR5 
SECTION: ".abs_section_57a"
  _TB2DSR6 
SECTION: ".abs_section_57b"
  _TB2DSR7 
SECTION: ".abs_section_57c"
  _TB2DLR 
SECTION: ".abs_section_57d"
  _TB2TBPR 

*********************************************************************************************
UNUSED-OBJECTS SECTION
---------------------------------------------------------------------------------------------
NOT USED PROCEDURES
main.c.o:
  PTDInit 
RTSHC08.C.o (ansif.lib):
  _PUSH_ARGS_L _PUSH_ARGS_D _ENTER_UNARY_L _ENTER_UNARY_L64 _ENTER_UNARY_L64_4 
  _ENTER_BINARY_L _ENTER_BINARY_L_RC _ENTER_BINARY_L_LC _ENTER_BINARY_L64 
  _ENTER_BINARY_L64_LC _ENTER_BINARY_L64_RC _LADD_k_is_k_plus_j 
  _k_is_k_plus_j_l _k_is_k_plus_j_i _LSUB_k_is_k_minus_j _LAND_k_is_k_and_j 
  _LOR_k_is_k_or_j _LXOR_k_is_k_xor_j _LMUL_k_is_k_mul_j _LDIVMOD _NEG_L_HX 
  _ABS_L_HX _SPLITSIGN_L _LMODU_k_is_k_mod_j _LDIVU_k_is_k_div_j 
  _LMODS_k_is_k_mod_j _LDIVS_k_is_k_div_j _LCMP_k_rel_j _BMULS _BDIVS _BMODS 
  _IMUL _IDIVU _IMODS _IMODU _IDIVU_8 _IMODU_8 _IASR _ILSR _ILSL _ICMP _LINC 
  _LDEC _LNEG _LNOT _LADD _LADD_RC _LSUB _LSUB_LC _LSUB_RC _LAND _LAND_RC _LOR 
  _LOR_RC _LXOR _LXOR_RC _LMUL _LMUL_RC _LDIVS _LDIVS_LC _LDIVS_RC _LDIVU 
  _LDIVU_LC _LDIVU_RC _LMODS _LMODS_LC _LMODS_RC _LMODU _LMODU_LC _LMODU_RC 
  _LASR _LLSR _LLSL _LCMP _LCMP_RC _COPY _COPY_L _POP32 _POP64 _STORE32 
  _STORE64 _SEXT8_32 _SEXT16_32 _CALL _Jump_Table_Addr _Jump_Table_Offset 
  _Jump_Table_Header_Addr _Search_Table_16_Addr _Search_Table_16_Offset 
  _Search_Table_8_Addr _Search_Table_8_Offset _PUSH_CC _POP_CC F_CLRK 
  F_CLRK_Unary F_NANK F_MAXK F_MAXK_Unary F_TLK F_XGKL _UNPACK_k_to_K 
  _UNPACK_k_to_K_Unary _UNPACK_j_to_L _PACK_K_to_k _PACK_K_to_k_Unary F_NORMK 
  _FADD_K_is_K_plus_L _FMUL_K_is_K_times_L _FDIV_K_is_K_div_L _F_LONGK 
  _F_FLOATK _FCMP_k_rel_j _FADD_Common _FSUB_Common _FMUL_Common _FDIV_Common 
  _FADD _FADD_RC _FSUB _FSUB_RC _FSUB_LC _FMUL _FMUL_RC _FDIV _FDIV_RC _FDIV_LC 
  _FSTRUNC _FUTRUNC _FNEG _FABS _FCMP _FCMP_RC _FINC _FDEC _FSFLOAT _FUFLOAT 
  D_TLK D_TLRes D_TKRes D_XGKL D_CLRK D_CLRK_Unary D_NANK D_NANK_Unary D_MAXK 
  D_MAXK_Unary _DUNPACK_k_to_K _DUNPACK_k_to_K_Unary _DUNPACK_j_to_L 
  _DPACK_K_to_k _DPACK_K_to_k_Unary D_NORMK_Unary D_NORMK _DADD_K_is_K_plus_L 
  _DMUL_K_is_K_times_L _DDIV_K_is_K_div_L _DCMP_k_rel_j _D_FLOATK _D_LONGK 
  _D_FTODK _D_DTOFK _DADD_Common _DSUB_Common _DMUL_Common _DDIV_Common _DADD 
  _DADD_RC _DSUB _DSUB_RC _DSUB_LC _DMUL _DMUL_RC _DDIV _DDIV_LC _DDIV_RC _DCMP 
  _DCMP_RC _DINC _DDEC _DNEG _DABS _DSFLOAT _DUFLOAT _DSTRUNC _DUTRUNC _DSHORT 
  _DLONG 
NOT USED VARIABLES
main.c.o:
  kp ki duty_chg_max duty_max kd AP_goal AP_last AP_error AP_error_last 
  AP_error_last2 duty_chg valve_in_flag valve_out_flag 
RTSHC08.C.o (ansif.lib):
  _PowOfTwo_8 _PowOfTwo_16 _PowOfTwo_32 plus1 minus1 plus1d minus1d errno 

*********************************************************************************************
COPYDOWN SECTION
---------------------------------------------------------------------------------------------
------- ROM-ADDRESS: 0xC3DB ---- SIZE       4 ---
Filling bytes inserted
 00010100
------- ROM-ADDRESS: 0xC3DF ---- RAM-ADDRESS: 0x100 ---- SIZE       1 ---
Name of initialized Object : ADchannel
 02
------- ROM-ADDRESS: 0xC3E0 ---- SIZE       2 ---
Filling bytes inserted
 0000

*********************************************************************************************
OBJECT-DEPENDENCIES SECTION
---------------------------------------------------------------------------------------------
Init                      USES _startupData loadByte 
_Startup                  USES _startupData __SEG_END_SSTACK Init 
systemboot                USES _CONFIG2 
TIM1Init                  USES _T1SC _T1SC0 _T1SC1 _T1MODH _T1MODL 
TIM2Init                  USES _T2SC _T2SC0 _T2SC1 _T2MODH _T2MODL 
ADInit                    USES _ADCLK _ADSCR 
SCIInit                   USES _SCC1 _SCC2 _SCC3 _SCBR _SCPSC 
IOInit                    USES _DDRA 
main                      USES systemboot TIM1Init TIM2Init ADInit SCIInit 
                                IOInit _PTD ADchannel _ADSCR _ADRL AP_now _ADRH 
                                Panel_now _SCS1 _SCDR SciRxdata 
                                _Jump_Table_Header_Offset delay _T2CH0 _T2CH1 abs_state _COPCTL main 
delay                     USES timer_10ms 
TIM1_Capture              USES _T1SC1 counter_now counter_bef _T1CH1H temp.1 
                                _T1CH1L counter _PTA 
TIM1_Overflow             USES _T1SC _PTA _SCC2 PutChar_SCI0 timer_10ms 
TIM2_Overflow             USES _T2SC _PTA 
SciTx                     USES TxDataNum _Jump_Table_Header_Offset AP_now 
                                _IDIVS Panel_now counter duty abs_state SciRxdata 
                                _T2CH0 _T2CH1 PutChar_SCI0 _SCC2 _PTA 
_SPLITSIGN                USES _IDIVMOD 
_IDIVS                    USES _SPLITSIGN 
PutChar_SCI0              USES _SCS1 _SCDR 
_Vector_14                USES SciTx 
_Vector_9                 USES TIM2_Overflow 
_Vector_6                 USES TIM1_Overflow 
_Vector_5                 USES TIM1_Capture 

*********************************************************************************************
DEPENDENCY TREE
*********************************************************************************************
 main and _Startup Group
 | 
 +- main                
 |  | 
 |  +- systemboot          
 |  |    
 |  +- TIM1Init            
 |  |    
 |  +- TIM2Init            
 |  |    
 |  +- ADInit              
 |  |    
 |  +- SCIInit             
 |  |    
 |  +- IOInit              
 |  |    
 |  +- _Jump_Table_Header_Offset
 |  |    
 |  +- delay               
 |       
 +- _Startup            
    | 
    +- Init                
       | 
       +- loadByte            
            
 _Vector_5           
 | 
 +- TIM1_Capture        
      
 _Vector_6           
 | 
 +- TIM1_Overflow       
    | 
    +- PutChar_SCI0        
         
 _Vector_9           
 | 
 +- TIM2_Overflow       
      
 _Vector_14          
 | 
 +- SciTx               
    | 
    +- _Jump_Table_Header_Offset (see above)
    |  
    +- _IDIVS              
    |  | 
    |  +- _SPLITSIGN          
    |     | 
    |     +- _IDIVMOD            
    |          
    +- PutChar_SCI0         (see above)
       
*********************************************************************************************
STATISTIC SECTION
---------------------------------------------------------------------------------------------

ExeFile:
--------
Number of blocks to be downloaded: 8
Total size of all blocks to be downloaded: 1004