📄 qam3118.h
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/****************************************************************
* File : qam3118.h
* Function : This file defines compiler constants and data structures
* used by qamlink.c. It is used to define the various
* register addresses in the BCM3118 chip.
* Author : P.J. Michalewicz
* History : 07/16/96 - PJM - Initial Coding
****************************************************************/
/************** Status Bit Assignments *****************
Bit 7: Acquision Mode (1=Auto , 0=Manual)
Bit 6: I2C / SPI Select (1=SPI , 0=I2C)
Bit 5: Script Error (1=Error , 0=OK)
Bit 4: QAM_Mode (Bit 2) 000 = QAM-4 001 = QAM-16
Bit 3: QAM_Mode (Bit 1) 010 = QAM-32 011 = QAM-64
Bit 2: QAM Mode (Bit 0) 100 = QAM-128 101 = QAM-256
Bit 1: FEC Lock Status (1=InLock , 0=NoLock)
Bit 0: QAM Lock Status (1=InLock , 0=NoLock)
*****************************************************************/
/* #define SUBSCRIBER_UNIT_CODE */
/* Status Reg Bit Assignments */
#define ACQUISITION_MODE 0x80 /* 1=Auto, 0=Manual */
#define SPI_SELECT 0x40 /* 1=SPI , 0=I2C */
#define RUNTIME_ERROR 0x20 /* 1=Error,0=OK */
#define FEC_LOCK_STATUS 0x02 /* 1=Lock, 0=NoLock */
#define QAM_LOCK_STATUS 0x01 /* 1=Lock, 0=NoLock */
/* useful macros */
#define QAM_IN_LOCK ((qam_status.status & QAM_LOCK_STATUS ) ? 1 : 0)
#define FEC_IN_LOCK ((qam_status.status & FEC_LOCK_STATUS ) ? 1 : 0)
#define SPI_MODE ((qam_status.status & SPI_SELECT ) ? 1 : 0)
#define QAM_MODE (0x7 & (qam_status.status >> 2))
#define SET_QAM_MODE(p1) qam_status.status = ((qam_status.status & 0xE3) | ((p1) << 2))
/* misc compiler constants */
#define SB_R 1 /* single-byte read reg */
#define SB_RW 3 /* single-byte read/write reg */
#define MB_R 5 /* multi-byte read reg */
#define MB_W 6 /* multi-byte write reg */
#define QAM_ERROR -1 /* error status */
#define QAM_OK 1 /* OK status */
#define QAM_UNKNOWN -1
#define TUNER_LOCK 1
#define TUNER_UNLOCK -1
/* default I2C Slave Address */
#ifndef SLAVE_ADDR
#define SLAVE_ADDR 0x0C /* I2C Bus Slave Address */
#endif
/* qam modes */
enum qam_mode_t {
QAM_4=0 ,
QAM_16 ,
QAM_32 ,
QAM_64 ,
QAM_128 ,
QAM_256
};
/* runtime errors */
enum errno_t {
NO_ERR=0 ,
I2C_NOACK , /* Acknowledge not seen on I2C transfer */
I2C_BAD_PROTO, /* Protocol violation on I2C bus */
SCR_ERROR , /* error in executing script file */
MAX_ERRNO
};
/* tuner types */
enum tuner_type_t {
SINGLE=0,
DOUBLE,
TEMIC
};
/* message types - note I2C does not use messages but */
/* acquisition scripts use these constants. Do not change !! */
enum msgtype_t {
MSG_DELAY=0 , /* delay specified time */
MSG_CONTROL , /* write qam control byte */
MSG_STATUS , /* read qamlink status */
MSG_WR_SB , /* single byte qam write */
MSG_RD_SB , /* single byte qam read */
MSG_WR_MB , /* multi byte qam write */
MSG_RD_MB , /* multi byte qam read */
MSG_NOACK , /* no acknowledge message */
MSG_ACK /* acknowledge message */
};
typedef unsigned char uchar;
typedef unsigned int uint;
/*
For SNR detector calibration; offset values to convert the
value for the number of FEC errors to an SNR based on the
average signal power for each constellation type
*/
#define OFFSET_QAM_4 76.307
#define OFFSET_QAM_16 77.276
#define OFFSET_QAM_32 76.765
#define OFFSET_QAM_64 77.488
#define OFFSET_QAM_128 76.872
#define OFFSET_QAM_256 77.539
/* Single Byte Register Identifiers */
#define SB_RSTCTL 0x105
#define SB_FRZCTL 0x106
#define SB_QAMCTL 0x107
#define SB_LMSCTL 0x108
#define SB_RTCCTL 0x109
#define SB_BYPCTL 0x10A
#define SB_FMTCTL 0x10B
#define SB_FFECTL 0x10C
#define SB_DSSCTL 0x10D
#define SB_IRQCTL 0x10E
#define SB_STOSCM 0x10F
#define SB_RSTCTR 0x110
#define SB_FRZCTL2 0x111
#define SB_RSVD2 0x112
#define SB_MASCTL 0x113
#define SB_TUNCTL 0x114
#define SB_EQLCTL 0x115
#define SB_RSCR0 0x1D0
#define SB_RSCR1 0x1D1
#define SB_RSCR2 0x1D2
#define SB_RSUR0 0x1D4
#define SB_RSUR1 0x1D5
#define SB_BCMPN0 0x1D6
#define SB_BCMPN1 0x1D7
#define SB_BCMPN2 0x1D8
#define SB_BCMRN 0x1D9
#define SB_RFCTL 0x1DA
#define SB_FECBYP 0x1DB
#define SB_PACLEN 0x1DC
#define SB_DATLEN 0x1DD
#define SB_RSWAT0 0x1DE
#define SB_RSWAT1 0x1DF
#define SB_SERPAR 0x1E0
#define SB_INTDEP 0x1E1
#define SB_INTWID 0x1E2
#define SB_INVSYN 0x1E3
#define SB_INTMEM 0x1E4
#define SB_MAXBAD 0x1E5
#define SB_MINGOO 0x1E6
#define SB_SYNCR1 0x1E7
#define SB_SYNCR2 0x1E8
#define SB_LRESWR 0x1E9
#define SB_LRESST 0x1EA
#define SB_LRESPO 0x1EB
#define SB_LRESPA 0x1EC
#define SB_SYNCR3 0x1ED
#define SB_HRMEVA 0x1EE
#define SB_SYNCR4 0x1EF
#define SB_SYNTST 0x1F0
#define SB_HRMCOU 0x1F1
#define SB_HRMDIS 0x1F2
#define SB_HRMPRBS 0x1F3
#define SB_HRMPAT 0x1F4
#define SB_HRMSEE 0x1F5
#define SB_SYNCR5 0x1F6
#define SB_SYNCR6 0x1F7
#define SB_BINVSYN 0x1F8
#define SB_INVSYT 0x1F9
#define SB_LSSYCT 0x1FA
#define SB_SYNSTA 0x1FB
#define SB_TUNSET 0x1FC
#define SB_CLKSET 0x1FD
#define SB_TUNSEL0 0x1FE
#define SB_TUNSEL1 0x1FF
/* Multi-Byte Register Addresses */
#define MBYTE0 0x00
#define MBYTE1 0x01
#define MBYTE2 0x02
#define MBYTE3 0x03
#define MBYTEOP 0x04
/* QAM Multi-Byte Op Codes */
#define MB_STF0 0x00 /* Store FFE Coefficient 0 */
#define MB_STF1 0x01 /* Store FFE Coefficient 1 */
#define MB_STF2 0x02 /* Store FFE Coefficient 2 */
#define MB_STF3 0x03 /* Store FFE Coefficient 3 */
#define MB_STF4 0x04 /* Store FFE Coefficient 4 */
#define MB_STF5 0x05 /* Store FFE Coefficient 5 */
#define MB_STF6 0x06 /* Store FFE Coefficient 6 */
#define MB_STF7 0x07 /* Store FFE Coefficient 7 */
#define MB_STD0 0x08 /* Store DFE Coefficient 0 */
#define MB_STD1 0x09 /* Store DFE Coefficient 1 */
#define MB_STD2 0x0A /* Store DFE Coefficient 2 */
#define MB_STD3 0x0B /* Store DFE Coefficient 3 */
#define MB_STD4 0x0C /* Store DFE Coefficient 4 */
#define MB_STD5 0x0D /* Store DFE Coefficient 5 */
#define MB_STD6 0x0E /* Store DFE Coefficient 6 */
#define MB_STD7 0x0F /* Store DFE Coefficient 7 */
#define MB_STSNRT 0x12 /* Store SNR Threshold */
#define MB_STSNRE 0x13 /* Store SNR Estimate */
#define MB_STSNRC 0x14 /* Store SNR Estimator val */
#define MB_STD8 0x1C /* Store DFE Coefficient 8 */
#define MB_STD9 0x1D /* Store DFE Coefficient 9 */
#define MB_STD10 0x1E /* Store DFE Coefficient 10 */
#define MB_STD11 0x1F /* Store DFE Coefficient 11 */
#define MB_STATHR 0x20 /* Store AGC Threshold */
#define MB_STABW 0x21 /* Store AGC Bandwidth */
#define MB_STAI 0x22 /* Store AGC Integrator */
#define MB_STIF 0x25 /* Store IF DC canceller integrator */
#define MB_STBBI 0x26 /* Store I rail baseband DC canceller integrator */
#define MB_STBBQ 0x27 /* Store Q rail baseband DC canceller integrator */
#define MB_STBRLC 0x28 /* Store Baud Linear Coeff */
#define MB_STBRIC 0x29 /* Store Baud Integ Coeff */
#define MB_STBRI 0x2A /* Store Baud Integrator */
#define MB_STBFOS 0x2B /* Store Baud Freq offset */
#define MB_STBEN 0x2C /* Enable Baud Loop */
#define MB_STBRDL 0x2D /* Store Baud recovery delay */
#define MB_STDRLC 0x30 /* Store Derotator linear coeff */
#define MB_STDRIC 0x31 /* Store Derotator integ coeff */
#define MB_STDRI 0x32 /* Store Derotator integrator ctl */
#define MB_STDRSP 0x33 /* Store Derotator sweep ctl */
#define MB_STDRPA 0x34 /* Store Derotator Phase Accum. */
#define MB_STDRRB 0x35 /* Store Derotator Soft Dec Thresh*/
#define MB_STDRFD 0x36 /* Store Derotator freq det thresh*/
#define MB_STGDSI 0x38 /* Store Derotator gp sigma delta */
#define MB_STOSC1 0x3B /* Store Derotator ctl PLL1 */
#define MB_STOSC2 0x3C /* Store Derotator ctl PLL2 */
#define MB_STLPST 0x3F /* Store Loop Status */
#define MB_LDF0 0x80 /* Load FFE Coefficient 0 */
#define MB_LDF1 0x81 /* Load FFE Coefficient 1 */
#define MB_LDF2 0x82 /* Load FFE Coefficient 2 */
#define MB_LDF3 0x83 /* Load FFE Coefficient 3 */
#define MB_LDF4 0x84 /* Load FFE Coefficient 4 */
#define MB_LDF5 0x85 /* Load FFE Coefficient 5 */
#define MB_LDF6 0x86 /* Load FFE Coefficient 6 */
#define MB_LDF7 0x87 /* Load FFE Coefficient 7 */
#define MB_LDD0 0x88 /* Load DFE Coefficient 0 */
#define MB_LDD1 0x89 /* Load DFE Coefficient 1 */
#define MB_LDD2 0x8A /* Load DFE Coefficient 2 */
#define MB_LDD3 0x8B /* Load DFE Coefficient 3 */
#define MB_LDD4 0x8C /* Load DFE Coefficient 4 */
#define MB_LDD5 0x8D /* Load DFE Coefficient 5 */
#define MB_LDD6 0x8E /* Load DFE Coefficient 6 */
#define MB_LDD7 0x8F /* Load DFE Coefficient 7 */
#define MB_LDSFT 0x90 /* Load Soft Decision */
#define MB_LDSNRE 0x93 /* Load SNR Estimate */
#define MB_LDIF 0x95 /* Load IF DC canceller integrator */
#define MB_LDBBI 0x96 /* Load I rail baseband DC canceller integrator */
#define MB_LDBBQ 0x97 /* Load Q rail baseband DC canceller integrator */
#define MB_LDD8 0x9C /* Load DFE Coefficient 8 */
#define MB_LDD9 0x9D /* Load DFE Coefficient 9 */
#define MB_LDD10 0x9E /* Load DFE Coefficient 10 */
#define MB_LDD11 0x9F /* Load DFE Coefficient 11 */
#define MB_LDALI 0xA0 /* Load AGC Leaky Integrator */
#define MB_LDAI 0xA1 /* Load AGC loop Integrator */
#define MB_LDADS 0xA2 /* Load AGC delta-sigma */
#define MB_LDBRFO 0xA4 /* Load Baud Filter Output */
#define MB_LDBRI 0xA5 /* Load Baud Integrator */
#define MB_LDBNCO 0xA6 /* Load baud NCO contents */
#define MB_LDBRDS 0xA7 /* Load baud delta-sigma */
#define MB_LDDRFO 0xA9 /* Load Derot Filter Output */
#define MB_LDDRI 0xAA /* Load Derot Integrator */
#define MB_LDDRPA 0xAB /* Load Derot Phase Accum. */
#define MB_LDGDS 0xAD /* Load Aux delta-Sigma */
#define MB_LDID 0xFF /* Chip ID information */
/* data structure to hold operational status for receiver */
/* BCM3118 mode settings gotten from single byte reads */
typedef struct qamstatus_t {
enum tuner_type_t tuner_used; /* choice of tuner */
uchar status; /* system status byte */
int errno; /* error status */
int scr_lineno; /* line # of script error */
float ref_freq; /* reference freq in MHz */
float symbol_rate; /* received symbol rate */
float lo_freq; /* local oscillator freq */
float snr_estimate; /* snr estimate in dB */
float ber_estimate; /* ber estimate */
float lock_thresh; /* lock threshold in dB */
float tnr_freq; /* tuner frequency in MHz */
char *acq_script; /* acquisition script */
char scr_buf[32]; /* for storing filename */
} qamstatus_t;
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