📄 user_if.c
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/* multi byte registers */
for (i=n=0; qam_keyword[i].keyword != (char *) 0; i++) {
if ((qam_keyword[i].r_w & 0x04) && (qam_keyword[i].r_w & 0x01)) {
x = 12 + 19 * (n / 10);
y = 14 + (n % 10);
j = 0xff & qam_keyword[i].keyval;
ip = (int *) &mb_data[j][0];
ip2 = (int *) &mb_data[j][2];
gotoxy(x,y); cprintf("%04x %04x",*ip,*ip2);
n++;
}
}
}
else
if (mode == DUMP_CONFIG) {
/* add code later */
}
else {
if (mode == DUMP_LOOPS) {
/* add code later */
if (dump_to_file) {
/* save this info to a file */
}
}
}
if (kbhit()) { /* F1-F10 for file store, tab to switch display, any other to exit */
i = getch();
if (i == 0x09) { /* tab key */
mode++;
if (mode > DUMP_LOOPS) mode = DUMP_RAW;
goto dump_refresh;
}
else
if (i == 0) {
switch (getch()) {
/*
case 0x54: cp = "data\\dump_f1.txt"; break;
case 0x55: cp = "data\\dump_f2.txt"; break;
case 0x56: cp = "data\\dump_f3.txt"; break;
case 0x57: cp = "data\\dump_f4.txt"; break;
case 0x58: cp = "data\\dump_f5.txt"; break;
case 0x59: cp = "data\\dump_f6.txt"; break;
case 0x5a: cp = "data\\dump_f7.txt"; break;
case 0x5b: cp = "data\\dump_f8.txt"; break;
case 0x5c: cp = "data\\dump_f9.txt"; break;
case 0x5d: cp = "data\\dump_f10.txt"; break;
*/
}
} else break;
}
delay(200); /* delay refresh a bit */
} /* end while */
}
void Init_FEC()
{
//#init the FEC
qam_write(SB_RW,SB_RSTCTL,0x40,0x00);//papi
qam_write(SB_RW,SB_DSSCTL,0x00,0x00);
qam_write(SB_RW,SB_TUNSEL0,0x00,0x00);// # set BERT board for FEC enabled
qam_write(SB_RW,SB_FECBYP,0x50,0x00);
qam_write(SB_RW,SB_MASCTL,0x0C,0x00);//papi
qam_write(SB_RW, SB_PACLEN,0xcb,0x00);
qam_write(SB_RW, SB_DATLEN,0xbb,0x00);
qam_write(SB_RW, SB_RSWAT0,0x02,0x00);
qam_write(SB_RW, SB_RSWAT1,0xbf,0x00);
#if 1
qam_write(SB_RW, SB_SERPAR,0x00,0x00);// # set for parallel output
qam_write(SB_RW, SB_INTDEP,0x0b,0x00);
qam_write(SB_RW, SB_INTWID,0x11,0x00);
qam_write(SB_RW, SB_INVSYN,0x03,0x00);
qam_write(SB_RW, SB_INTMEM,0x00,0x00);
qam_write(SB_RW, SB_MAXBAD,0x38,0x00);
qam_write(SB_RW, SB_MINGOO,0x5f,0x00);
qam_write(SB_RW, SB_SYNCR1,0xa8,0x00);
qam_write(SB_RW, SB_SYNCR2,0x2d,0x00);
qam_write(SB_RW, SB_LRESWR,0xca,0x00);
qam_write(SB_RW, SB_LRESST,0x00,0x00);
qam_write(SB_RW, SB_LRESPO,0x01,0x00);
qam_write(SB_RW, SB_LRESPA,0x47,0x00);
qam_write(SB_RW, SB_SYNCR3,0x32,0x00);
qam_write(SB_RW, SB_HRMEVA,0x5d,0x00);
qam_write(SB_RW, SB_SYNCR4,0x3c,0x00);
qam_write(SB_RW, SB_SYNTST,0x01,0x00);
qam_write(SB_RW, SB_HRMCOU,0xca,0x00);
qam_write(SB_RW, SB_HRMDIS,0xca,0x00);
qam_write(SB_RW, SB_HRMPRBS,0x63,0x00);
qam_write(SB_RW, SB_HRMPAT,0x4b,0x00);
qam_write(SB_RW, SB_HRMSEE,0x01,0x00);
qam_write(SB_RW, SB_SYNCR5,0x59,0x00);
qam_write(SB_RW, SB_SYNCR6,0xea,0x00);
qam_write(SB_RW, SB_BINVSYN,0x1f,0x00);
qam_write(SB_RW, SB_INVSYT,0x1f,0x00);
qam_write(SB_RW, SB_LSSYCT,0x11,0x00);
qam_write(SB_RW, SB_SYNCR4,0x3d,0x00);
#endif
}
void Init_Config()
{
qam_write(SB_RW,SB_FRZCTL,0xfe,0x00);//qam_write frzctl 0xfe# freeze all but AGC
qam_write(SB_RW,SB_RSTCTL,0x7f,0x00);//# reset all
qam_write(SB_RW,SB_RSTCTR,0x01,0x00);// papi caution
qam_write(SB_RW,SB_RSTCTR,0x00,0x00);// papi caution
qam_write(MB_W, MB_STF7, 0x5800, 0x0000);// papi preload main tap to max real, zero imag
qam_write(SB_RW,SB_FFECTL,0x3f,0x00); //papi
qam_write(SB_RW,SB_LMSCTL,0x0b,0x00); // LMS step size 2^-10DFE, 2^-9 FFE
qam_write(SB_RW,SB_RTCCTL,0xd7,0x00); // I2C glitch delay enabled, test port disable
qam_write(SB_RW,SB_BYPCTL,0x80,0x00); // enable all receiver functions, squelch tuner clock
if( Normal == 1)//normal spectrum
qam_write(SB_RW,SB_FMTCTL,0x0C,0x00); // enable ADCLK, diff and Gray decoding, internal A/D w/ offset binary
if(Normal == 0)
qam_write(SB_RW,SB_FMTCTL,0x04,0x00); // enable ADCLK, diff and Gray decoding, internal A/D w/ offset binary
qam_write(SB_RW,SB_IRQCTL,0x00,0x00); // mask off all interrupts
qam_write(MB_W,MB_STDRRB,0x0000,0x0000);// disable robust derotator operation
switch(Select_QAM)
{
case QAM_4:
qam_write(MB_W,MB_STDRFD,0x9000,0x0000);// disable frequency detector
break;
default:
qam_write(MB_W,MB_STDRFD,0x0000,0x0000);// disable frequency detector
break;
}
qam_write(MB_W,MB_STBRDL,0x0000,0x0000); // papi # enable auto baud delay generation
qam_write(SB_RW,SB_FRZCTL2,0x10,0x00);// enable DC offset cancellation
switch (Select_QAM) {
case QAM_4 :
qam_write(SB_RW,SB_QAMCTL,0x00,0x00);
break;
case QAM_16 :
qam_write(SB_RW,SB_QAMCTL,0x00,0x00);
break;
case QAM_32 :
qam_write(SB_RW,SB_QAMCTL,0x00,0x00);
break;
case QAM_64 :
qam_write(SB_RW,SB_QAMCTL,0x00,0x00);
break;
case QAM_128:
qam_write(SB_RW,SB_QAMCTL,0x12,0x00);// 32QAM
break;
case QAM_256:
qam_write(SB_RW,SB_QAMCTL,0x00,0x00);// QPSK 0x00
break;
}
qam_write(SB_RW,SB_STOSCM,0x1a,0x00);// papi use PLL1 = 8*xtal,use PLL1 as IF_OSC
qam_write(MB_W,MB_STATHR,0x0a00,0x0000);// set AGC initial power threshold (set again later)
qam_write(MB_W,MB_STABW,0x0800,0x0000);// set AGC BW for moderate rate, positive sense
qam_write(MB_W, MB_STAI,0x0000,0x0000);// set AGC to mid scale
qam_write(MB_W,MB_STBRLC,0x2170,0x0000);// set baud bandwidth large
qam_write(MB_W,MB_STBRIC,0x06b0,0x0000);//
qam_write(MB_W,MB_STBRI,0x0000,0x0000);//papi.... exchange STBRI....
qam_write(MB_W,MB_STBEN,0x0100,0x0000);// enable baud loop w/ 1-phase time constant
//qam_write stdrlc 0xc000 # set the derotator to wide bandwidth
qam_write(MB_W,MB_STDRLC,0xf000,0x0000);// set the derotator to wide bandwidth
//#qam_write stdric 0xc000 #
qam_write(MB_W,MB_STDRIC,0xf000,0x0000);
qam_write(MB_W,MB_STDRI,0x0000,0x0000); // set derotator to zero on reset
qam_write(MB_W,MB_STDRSP,0x0000,0x0000);// set phase accumulator to zero on reset
qam_write(MB_W,MB_STSNRC,0x0300,0x0000);// set fast response on SNR estimator
qam_write(MB_W,MB_STSNRT,0x2000,0x0000);// SNR threshold for generating interrupts
qam_write(SB_RW,SB_RSTCTL,0x1f,0x00);// reset all loops with programmed integrators
}
void Acquire_Baud_Timing()
{
//### Acquire Baud Timing ###
qam_write(SB_RW,SB_FRZCTL,0x39,0x00);// enable baud and derot only
delay(50+gap);
qam_write(MB_W,MB_STBRLC,0x0617,0x0000);
qam_write(MB_W,MB_STBRIC,0x012b,0x0000);
delay(20+gap);
qam_write(MB_W,MB_STBRLC,0x0217,0x0000);
qam_write(MB_W,MB_STBRIC,0x006b,0x0000);
delay(10+gap);
qam_write(MB_W,MB_STBRLC,0x0042,0x0000);
qam_write(MB_W,MB_STBRIC,0x000c,0x0000);
delay(10+gap);
qam_write(MB_W,MB_STBRLC,0x0056,0x0000);
qam_write(MB_W,MB_STBRIC,0x0003,0x0000);
delay(20+gap);
}
void Constellation_4_Refinement()
{
qam_write(SB_RW,SB_FRZCTL,0x21,0x00);
qam_write(SB_RW,SB_QAMCTL,0x09,0x00);//# 16 QAM errors and decisions
delay (30+gap);
qam_write(MB_W,MB_STDRLC,0xf000,0x0000);// # reduce carrier BW
/*papi*/qam_write(MB_W,MB_STDRIC,0xf400,0x0000);// # reduce carrier BW
delay(10+gap);
qam_write(MB_W,MB_STDRLC,0xf400,0x0000);// # reduce carrier BW
/*papi*/qam_write(MB_W,MB_STDRIC,0xfc00,0x0000);// # reduce carrier BW
qam_write(MB_W,MB_STF7,0x6000,0x0000);// # reduce carrier BW
qam_write(SB_RW,SB_FRZCTL,0x21,0x00);
//papi 256 change 99.4.7
qam_write(SB_RW,SB_QAMCTL,0x00,0x00);
delay (20+gap);
qam_write(MB_W,MB_STBRLC,0x0028,0x0000);
qam_write(MB_W,MB_STBRIC,0x0001,0x0000);
delay (20+gap);
qam_write(MB_W,MB_STDRLC,0xf9c0,0x0000);// # 15 kHz BW
qam_write(MB_W,MB_STDRIC,0xf840,0x0000);
qam_write(SB_RW,SB_FRZCTL,0x20,0x00);
}
void Constellation_16_Refinement()
{
qam_write(SB_RW,SB_FRZCTL,0x21,0x00);
qam_write(SB_RW,SB_QAMCTL,0x09,0x00);//# 16 QAM errors and decisions
delay (30+gap);
qam_write(MB_W,MB_STDRLC,0xf000,0x0000);// # reduce carrier BW
/*papi*/qam_write(MB_W,MB_STDRIC,0xf400,0x0000);// # reduce carrier BW
delay(10+gap);
qam_write(MB_W,MB_STDRLC,0xf400,0x0000);// # reduce carrier BW
/*papi*/qam_write(MB_W,MB_STDRIC,0xfc00,0x0000);// # reduce carrier BW
qam_write(MB_W,MB_STF7,0x6000,0x0000);// # reduce carrier BW
qam_write(SB_RW,SB_FRZCTL,0x21,0x00);
//papi 256 change 99.4.7
qam_write(SB_RW,SB_QAMCTL,0x09,0x00);
delay (20+gap);
qam_write(MB_W,MB_STBRLC,0x0028,0x0000);
qam_write(MB_W,MB_STBRIC,0x0001,0x0000);
delay (20+gap);
qam_write(MB_W,MB_STDRLC,0xf9c0,0x0000);// # 15 kHz BW
qam_write(MB_W,MB_STDRIC,0xf840,0x0000);
qam_write(SB_RW,SB_FRZCTL,0x20,0x00);
}
void Constellation_64_Refinement()
{
qam_write(SB_RW,SB_FRZCTL,0x21,0x00);
qam_write(SB_RW,SB_QAMCTL,0x09,0x00);//# 16 QAM errors and decisions
delay (30+gap);
qam_write(MB_W,MB_STDRLC,0xf400,0x0000);// # reduce carrier BW
qam_write(MB_W,MB_STF7,0x6000,0x0000);// # reduce carrier BW
qam_write(SB_RW,SB_FRZCTL,0x21,0x00);
//papi 256 change 99.4.7
switch (Select_QAM) {
case QAM_4 :
qam_write(SB_RW,SB_QAMCTL,0x00,0x00);
break;
case QAM_16 :
qam_write(SB_RW,SB_QAMCTL,0x09,0x00);
break;
case QAM_32 :
qam_write(SB_RW,SB_QAMCTL,0x12,0x00);
break;
case QAM_64 :
qam_write(SB_RW,SB_QAMCTL,0x1b,0x00);
break;
case QAM_128:
qam_write(SB_RW,SB_QAMCTL,0x24,0x00);
break;
case QAM_256:
qam_write(SB_RW,SB_QAMCTL,0x2d,0x00);
break;
}
delay (20+gap);
qam_write(MB_W,MB_STBRLC,0x0028,0x0000);
qam_write(MB_W,MB_STBRIC,0x0001,0x0000);
delay (20+gap);
qam_write(MB_W,MB_STDRLC,0xf900,0x0000);// # 15 kHz BW
qam_write(MB_W,MB_STDRIC,0xf100,0x0000);
qam_write(SB_RW,SB_FRZCTL,0x20,0x00);
}
void Constellation_32_Refinement()
{
qam_write(SB_RW,SB_FRZCTL,0x21,0x00);
qam_write(SB_RW,SB_QAMCTL,0x09,0x00);//# 16 QAM errors and decisions
delay (30+gap);
qam_write(MB_W,MB_STDRLC,0xf000,0x0000);// # reduce carrier BW
/*papi*/qam_write(MB_W,MB_STDRIC,0xf400,0x0000);// # reduce carrier BW
delay(10+gap);
qam_write(MB_W,MB_STDRLC,0xf400,0x0000);// # reduce carrier BW
/*papi*/qam_write(MB_W,MB_STDRIC,0xfc00,0x0000);// # reduce carrier BW
qam_write(MB_W,MB_STF7,0x6000,0x0000);// # reduce carrier BW
qam_write(SB_RW,SB_FRZCTL,0x21,0x00);
//papi 256 change 99.4.7
qam_write(SB_RW,SB_QAMCTL,0x12,0x00);
delay (20+gap);
qam_write(MB_W,MB_STBRLC,0x0028,0x0000);
qam_write(MB_W,MB_STBRIC,0x0001,0x0000);
delay (20+gap);
qam_write(MB_W,MB_STDRLC,0xf9c0,0x0000);// # 15 kHz BW
qam_write(MB_W,MB_STDRIC,0xf840,0x0000);
qam_write(SB_RW,SB_FRZCTL,0x20,0x00);
}
void Constellation_128_Refinement()
{
qam_write(SB_RW,SB_FRZCTL,0x21,0x00);
qam_write(SB_RW,SB_QAMCTL,0x09,0x00);//# 16 QAM errors and decisions
delay (30+gap);
qam_write(MB_W,MB_STDRLC,0xf000,0x0000);// # reduce carrier BW
/*papi*/qam_write(MB_W,MB_STDRIC,0xf400,0x0000);// # reduce carrier BW
delay(10+gap);
qam_write(MB_W,MB_STDRLC,0xf400,0x0000);// # reduce carrier BW
/*papi*/qam_write(MB_W,MB_STDRIC,0xfc00,0x0000);// # reduce carrier BW
qam_write(MB_W,MB_STF7,0x6000,0x0000);// # reduce carrier BW
qam_write(SB_RW,SB_FRZCTL,0x21,0x00);
//papi 256 change 99.4.7
qam_write(SB_RW,SB_QAMCTL,0x24,0x00);
delay (20+gap);
qam_write(MB_W,MB_STBRLC,0x0028,0x0000);
qam_write(MB_W,MB_STBRIC,0x0001,0x0000);
delay (20+gap);
qam_write(MB_W,MB_STDRLC,0xf9c0,0x0000);// # 15 kHz BW
qam_write(MB_W,MB_STDRIC,0xf840,0x0000);
qam_write(SB_RW,SB_FRZCTL,0x20,0x00);
}
void Constellation_256_Refinement()
{
qam_write(SB_RW,SB_FRZCTL,0x21,0x00);
qam_write(SB_RW,SB_QAMCTL,0x09,0x00);//# 16 QAM errors and decisions
delay (30+gap);
qam_write(MB_W,MB_STDRLC,0xf400,0x0000);// # reduce carrier BW
qam_write(MB_W,MB_STF7,0x6000,0x0000);// # reduce carrier BW
qam_write(SB_RW,SB_FRZCTL,0x21,0x00);
//papi 256 change 99.4.7
qam_write(SB_RW,SB_QAMCTL,0x2d,0x00);
delay (20+gap);
qam_write(MB_W,MB_STBRLC,0x0028,0x0000);
qam_write(MB_W,MB_STBRIC,0x0001,0x0000);
delay (20+gap);
qam_write(MB_W,MB_STDRLC,0xf900,0x0000);// # 15 kHz BW
qam_write(MB_W,MB_STDRIC,0xf100,0x0000);
qam_write(SB_RW,SB_FRZCTL,0x20,0x00);
}
/********************************************************************
* run_command_file - accepts a limited set of commands from the
* specified file and executes them. If the file pointer is stdin,
* commands are read from the keyboard.
*********************************************************************/
int run_command_file(FILE *fp)
{
unsigned int thresh_msbs;
int argc,done=0,reg,ival,qval,rstat;
int pll1_div,pll2_div;
char line[80],*argv[8],*cp,tmpbuf[80];
enum ShellCmdType cmd;
float fval, offset;
double dval;
long lval;
extern int com_initialized;
clrscr();
if (fp == stdin) {
printf("--- Command Line Mode Entered ---\n");
printf("Available Commands : qam_write register value\n");
printf(" : qam_read register \n");
printf(" : qam_init \n");
printf(" : help \n");
printf(" : set parameter value \n");
printf(" : exit (to return to menu)\n");
printf("QAM > ");
}
while (!done && (fgets(line,80,fp) != (char *) NULL)) {
/* convert to lower case */
for (cp = line; *cp != '\0'; cp++) *cp = tolower(*cp);
/* echo command to screen */
if (fp != stdin) printf("QAM > %s",line);
cmd = parse(line,&argc,argv);
switch (cmd) {
case SHELL_QAM_READ :
case SHELL_QAM_WRITE:
reg = qam_lookup(argv[1]);
if ( (reg == QAM_UNKNOWN) ||
((cmd == SHELL_QAM_WRITE) && (argc < 3)) ||
((cmd == SHELL_QAM_READ ) && (argc != 2))) {
printf("QAM > ^--- Syntax Error\n");
}
else {
ival = qval = 0;
if (argc >= 3) sscanf(argv[2],"%x",&ival);
if (argc >= 4) sscanf(argv[3],"%x",&qval);
if (cmd == SHELL_QAM_WRITE) {
rstat = qam_write(access,reg,ival,qval);
}
else {
rstat = qam_read(access,reg,&ival,&qval);
if (rstat != QAM_ERROR) {
if ((reg >= MB_LDF0) && (reg <= MB_LDD7)) {
printf("QAM > %s = 0x%04x 0x%04x\n",argv[1],ival,qval);
}
else {
printf("QAM > %s = 0x%04x\n",argv[1],ival);
}
}
}
if (rstat == QAM_ERROR) printf("QAM > ^--- Syntax Error\n");
}
break;
case SHELL_HELP: help_code();
clrscr();
break;
case SHELL_EXIT: done = 1;
break;
case SHELL_PROMPT: if (argc > 1) printf("%s",argv[1]);
gets(tmpbuf);
break;
case SHELL_QAM_INIT: rstat = qam_init(qam_status.acq_script);
if (rstat == QAM_ERROR) {
cprintf("Error in execution of '%s' ... hit rtn", line);
gets(tmpbuf);
}
break;
case SHELL_PING:
if ((argv[1][0] == '0') && (argv[1][1] == 'x')) {
sscanf(argv[1],"%x",&ival);
}
else {
sscanf(argv[1],"%d",&ival);
}
i2c_ping(ival);
break;
case SHELL_SET: //setting program
if (strncmp(argv[1],"lock_thresh",11) == 0) {
sscanf(argv[2],"%f",&qam_status.lock_thresh);
/*
Now that we've read in what the lock_thresh
is we will convert from dB to linear scale
and feed it back to the 3118 so that it can
internally determine if the SNR is above this
chosen threshold and set the appropriate bit
in the IRQ register.
*/
switch (QAM_MODE) {
case QAM_4 : offset = OFFSET_QAM_4; break;
case QAM_16 : offset = OFFSET_QAM_16; break;
case QAM_32 : offset = OFFSET_QAM_32; break;
case QAM_64 : offset = OFFSET_QAM_64; break;
case QAM_128 : offset = OFFSET_QAM_128; break;
case QAM_256 : offset = OFFSET_QAM_256; break;
}
fval = pow(10.0, -(qam_status.lock_thresh - offset)/20.0);
thresh_msbs = (unsigned int) fval;
ival = thresh_msbs;
/* store unsigned value in a signed variable */
/* only 16 bits of the 24 bit multi-byte register will be specified */
qam_write(MB_W,MB_STSNRT,ival,0);
}
else
if (strncmp(argv[1],"acq_script" ,10) == 0) {
sscanf(argv[2],"%s",qam_status.scr_buf);
qam_status.acq_script = qam_status.scr_buf;
}
else
if (strncmp(argv[1],"acq_mode",8) == 0) {
if (strncmp(argv[2],"auto",4) == 0)
qam_status.status |= ACQUISITION_MODE;
if (strncmp(argv[2],"manual",6) == 0)
qam_status.status &= ~ACQUISITION_MODE;
}
else
if (strncmp(argv[1],"slave_addr",10) == 0) {
sscanf(argv[2],"%x",&glb_slave_addr);
}
else
if (strncmp(argv[1],"port_data",9) == 0) {
sscanf(argv[2],"%x",&glb_port_data);
glb_port_status = glb_port_data + 1;
glb_port_control = glb_port_data + 2;
}
else
if (strncmp(argv[1],"bus_type",8) == 0) {
if (strcmp(argv[2],"spi") == 0) {
qam_status.status |= SPI_SELECT;
com_initialized = 0;
}
else {
qam_status.status &= ~SPI_SELECT;
com_initialized = 0;
}
}
else
if (strncmp(argv[1],"ref_freq",8) == 0) {
sscanf(argv[2],"%f",&qam_status.ref_freq);
}
else
if (strncmp(argv[1],"symbol_rate",11) == 0) {
/* this sets the received symbol rate*/
/* STBFOS = 0x1000000*(symbol_rate/ref_freq) 24 bit */
sscanf(argv[2],"%f",&fval);
dval = 1.6777216e7 * fval / qam_status.ref_freq;
lval = (long) dval;
ival = lval >> 8;
qval = 0xff00 & (lval << 8);//24 bit
qam_write(MB_W,MB_STBEN,0,0);
qam_write(MB_W,MB_STBFOS,ival,qval);
qam_write(MB_W,MB_STBEN,0x0100,0);
}
else
if (strncmp(argv[1],"lo_freq",7) == 0) {
sscanf(argv[2],"%f",&fval);
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