tsk3000_load_from_flash.prjfpg

TSK3000 Load From Flash Altium Designer 编译通过.

[Design]
Version=1.0
HierarchyMode=0
ChannelRoomNamingStyle=0
OutputPath=Out
ChannelDesignatorFormatString=$Component_$RoomName
ChannelRoomLevelSeperator=_
OpenOutputs=1
ArchiveProject=0
TimestampOutput=0
SeparateFolders=0
AllowPortNetNames=0
AllowSheetEntryNetNames=1
AppendSheetNumberToLocalNets=0
DefaultConfiguration=
UserID=0xFFFFFFFF
DefaultPcbProtel=1
DefaultPcbPcad=0
ReorderDocumentsOnCompile=1
VHDL87=0
Verilog95=0

[Document1]
DocumentPath=TSK3000_Load_From_Flash.SchDoc
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None

[Document2]
DocumentPath=TSK3000_Load_From_Flash.Constraint
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None

[Document3]
DocumentPath=NB1_6_EP1C12Q240.Constraint
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None

[Document4]
DocumentPath=NB1_6_XC3S1000-FG456.Constraint
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None

[Document5]
DocumentPath=NB1_6_EP1C20F400C8.Constraint
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None

[Document6]
DocumentPath=NB1_6_EP1S10F780.Constraint
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None

[Document7]
DocumentPath=NB1_6_XC2S600E_6FG456C.Constraint
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None

[Document8]
DocumentPath=NB1_6_XC2V1000-4FG456.Constraint
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None

[Document9]
DocumentPath=NB1_6_XC2VP7-FG456.Constraint
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None

[Configuration1]
Name=Cyclone-12_NB1
ParameterCount=0
ConstraintFileCount=2
ConstraintFilePath1=NB1_6_EP1C12Q240.Constraint
ConstraintFilePath2=TSK3000_Load_From_Flash.Constraint

[Configuration2]
Name=Cyclone-20_NB1
ParameterCount=0
ConstraintFileCount=2
ConstraintFilePath1=NB1_6_EP1C20F400C8.Constraint
ConstraintFilePath2=TSK3000_Load_From_Flash.Constraint

[Configuration3]
Name=Spartan2E-600_NB1
ParameterCount=0
ConstraintFileCount=2
ConstraintFilePath1=NB1_6_XC2S600E_6FG456C.Constraint
ConstraintFilePath2=TSK3000_Load_From_Flash.Constraint

[Configuration4]
Name=Spartan3-1000_NB1
ParameterCount=0
ConstraintFileCount=2
ConstraintFilePath1=NB1_6_XC3S1000-FG456.Constraint
ConstraintFilePath2=TSK3000_Load_From_Flash.Constraint

[Configuration5]
Name=Stratix-10_NB1
ParameterCount=0
ConstraintFileCount=2
ConstraintFilePath1=NB1_6_EP1S10F780.Constraint
ConstraintFilePath2=TSK3000_Load_From_Flash.Constraint

[Configuration6]
Name=Virtex2-1000_NB1
ParameterCount=0
ConstraintFileCount=2
ConstraintFilePath1=NB1_6_XC2V1000-4FG456.Constraint
ConstraintFilePath2=TSK3000_Load_From_Flash.Constraint

[Configuration7]
Name=Virtex2Pro-7_NB1
ParameterCount=0
ConstraintFileCount=2
ConstraintFilePath1=NB1_6_XC2VP7-FG456.Constraint
ConstraintFilePath2=TSK3000_Load_From_Flash.Constraint

[Generic_Quartus_sh]
Configuration Device - Stratix=AUTO
Configuration Device - Cyclone=AUTO
Configuration Scheme - Stratix=PASSIVE_SERIAL
Fast FIT Compilation=True
Ignore Clock Settings=False
Optimize Timing=NORMAL COMPILATION
Configuration Device=AUTO
Configuration Scheme=PASSIVE_SERIAL
Optimization Technique=BALANCED
Register Packing=NORMAL
Fitter Effort=AUTO FIT

[Generic_VHDLSimulation]
Tool=DXP Simulator
NoIEEE=False
VHDL93=True
Verilog2001=True
TopLevelEntity=
TopLevelArchitecture=
TopLevelUnit=Select a testbench document
RunToTime=100000000
SDFInstance=
SDFFileName=
SDFOptimization=1
SettingsModified=False
TimeStep=100000000
TimeUnits=ns
RunToUnits=ns

[Generic_MapMAP]
Pack CLBs=100
Cover Mode=Area
Map to Input Functions=4
Turn Off Logic Replication=False
No Register Ordering=False
Allow Register Packing In I/O=True
Pack Registers in I/O=b
Timing-Driven Packing=False
Transform Buses=off
Do Not Remove Unused Logic=False

[Generic_Place & RoutePAR]
Overall Effort Level=med
Used Bonded IOs=True
Ignore Timing Constraints=False
Advanced Analysis=True
Report Fastest Paths=False
Limit Timing Report=100
Report Uncovered Paths=3

[Generic_VHDLSynthesis]
Tool=Altium Synthesizer
SettingsModified=False
Entity=
Architecture=
PromptedNewSynthesizer=False
SchematicNetlister=0
Insert IO Buffers=True
Default Enumeration Encoding=Default
Resource Sharing=True
FSM Compiler=True
Maximum Fanout=100
Optimization Goal=Area
Optimization Level=2
Frequency=0
Don't push Tristates across Process/Block boundaries=True
Keep Hierarchy=True
Infer Macrocells=False
Macrocell Kind=Coregen
Map Logic=True
Pack IO Registers into IOBs=Auto
Ram Style=Auto
Register Duplication=True
Write Mapped VHDL Netlist=False
Write Mapped Verilog Netlist=False
Write Vendor Constraint File=True
Include Synopsys Library=True
Include IEEE Numeric STD Library=False
Report Inferred Operators=False
Report Optimization Messages=False

[OutputGroup1]
Name=Netlist Outputs
Description=
PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintWhat=1
OutputType1=EDIF
OutputName1=EDIF for PCB
OutputDocumentPath1=
OutputEnabled1=1
OutputDefault1=0
OutputType2=MultiWire
OutputName2=MultiWire
OutputDocumentPath2=
OutputEnabled2=1
OutputDefault2=0
OutputType3=Pcad
OutputName3=Pcad for PCB
OutputDocumentPath3=
OutputEnabled3=1
OutputDefault3=0
OutputType4=ProtelNetlist
OutputName4=Protel
OutputDocumentPath4=
OutputEnabled4=1
OutputDefault4=0
OutputType5=VHDL
OutputName5=VHDL File
OutputDocumentPath5=
OutputEnabled5=1
OutputDefault5=0
Configuration5_Name1=OutputConfigurationParameter1
Configuration5_Item1=Crossprobe=False|EnableAttributes=True|Record=VHDLView|SingleFile=True
OutputType6=XSpiceNetlist
OutputName6=XSpice Netlist
OutputDocumentPath6=
OutputEnabled6=1
OutputDefault6=0
OutputType7=Verilog
OutputName7=Verilog File
OutputDocumentPath7=
OutputEnabled7=1
OutputDefault7=0

[OutputGroup2]
Name=Simulator Outputs
Description=
PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintWhat=1
OutputType1=AdvSimNetlist
OutputName1=Mixed Sim
OutputDocumentPath1=