c6000.h

ND-Tech DSP 6713 Motor Control Source

#define EXT_INT7	0x7		// GPIO interrupt 7/External interrupt pin 7
#define EDMA_INT	0x8		// EDMA channel (0 through 63) interrupt
#define	XINT0		0xc		// McBSP 0 transmit interrupt
#define	RINT0		0xd		// McBSP 0 receive interrupt
#define	XINT1		0xe		// McBSP 1 transmit interrupt
#define	RINT1		0xf		// McBSP 1 receive interrupt
#define	GPINT0		0x10	// GPIO interrupt 0
#define	XINT2		0x11	// McBSP 2 transmit interrupt
#define	RINT2		0x12	// McBSP 2 receive interrupt
#define	TINT2		0x13	// Timer 2 interrupt
#define	SD_INTB		0x14	// EMIFB SDRAM timer interrupt
#define PCI_WAKEUP	0x15	// PCI wakeup interrupt
#define UINT		0x17	// UTOPIA interrupt
#endif


/*	DMA Registers	*/
#ifdef _C6701_
#define DMA_PRICTL0		*(volatile int *)0x01840000	// DMA channel 0 priority control register
#define DMA_SECCTL0		*(volatile int *)0x01840008	// DMA channel 0 secondary control register
#define DMA_SRC0		*(volatile int *)0x01840010	// DMA channel 0 source address
#define DMA_DST0		*(volatile int *)0x01840018	// DMA channel 0 destination address
#define DMA_XFRCNT0		*(volatile int *)0x01840020	// DMA channel 0 transfer counter
#define DMA_PRICTL1		*(volatile int *)0x01840040	// DMA channel 1 priority control register
#define DMA_SECCTL1		*(volatile int *)0x01840048	// DMA channel 1 secondary control register
#define DMA_SRC1		*(volatile int *)0x01840050	// DMA channel 1 source address
#define DMA_DST1		*(volatile int *)0x01840058	// DMA channel 1 destination address
#define DMA_XFRCNT1		*(volatile int *)0x01840060	// DMA channel 1 transfer counter
#define DMA_PRICTL2		*(volatile int *)0x01840004	// DMA channel 2 priority control register
#define DMA_SECCTL2		*(volatile int *)0x0184000C	// DMA channel 2 secondary control register
#define DMA_SRC2		*(volatile int *)0x01840014	// DMA channel 2 source address
#define DMA_DST2		*(volatile int *)0x0184001C	// DMA channel 2 destination address
#define DMA_XFRCNT2		*(volatile int *)0x01840024	// DMA channel 2 transfer counter
#define DMA_PRICTL3		*(volatile int *)0x01840044	// DMA channel 3 priority control register
#define DMA_SECCTL3		*(volatile int *)0x0184004C	// DMA channel 3 secondary control register
#define DMA_SRC3		*(volatile int *)0x01840054	// DMA channel 3 source address
#define DMA_DST3		*(volatile int *)0x0184005C	// DMA channel 3 destination address
#define DMA_XFRCNT3		*(volatile int *)0x01840064	// DMA channel 3 transfer counter
#define	DMA_AUXCTL		*(volatile int *)0x01840070	// DMA auxiliary control register
#define	DMA_GBLADDRA	*(volatile int *)0x01840038	// DMA global address register A
#define	DMA_GBLADDRB	*(volatile int *)0x0184003C	// DMA global address register B
#define	DMA_GBLADDRC	*(volatile int *)0x01840068	// DMA global address register C
#define	DMA_GBLADDRD	*(volatile int *)0x0184006C	// DMA global address register D
#define	DMA_GBLCNTA		*(volatile int *)0x01840028	// DMA global count reload register A
#define	DMA_GBLCNTB		*(volatile int *)0x0184002C	// DMA global count reload register B
#define	DMA_GBLIDXA		*(volatile int *)0x01840030	// DMA global index register A
#define	DMA_GBLIDXB		*(volatile int *)0x01840034	// DMA global index register B
#endif

#ifdef _C6203_
#define DMA_PRICTL0		*(volatile int *)0x01840000	// DMA channel 0 priority control register
#define DMA_SECCTL0		*(volatile int *)0x01840008	// DMA channel 0 secondary control register
#define DMA_SRC0		*(volatile int *)0x01840010	// DMA channel 0 source address
#define DMA_DST0		*(volatile int *)0x01840018	// DMA channel 0 destination address
#define DMA_XFRCNT0		*(volatile int *)0x01840020	// DMA channel 0 transfer counter
#define DMA_PRICTL1		*(volatile int *)0x01840040	// DMA channel 1 priority control register
#define DMA_SECCTL1		*(volatile int *)0x01840048	// DMA channel 1 secondary control register
#define DMA_SRC1		*(volatile int *)0x01840050	// DMA channel 1 source address
#define DMA_DST1		*(volatile int *)0x01840058	// DMA channel 1 destination address
#define DMA_XFRCNT1		*(volatile int *)0x01840060	// DMA channel 1 transfer counter
#define DMA_PRICTL2		*(volatile int *)0x01840004	// DMA channel 2 priority control register
#define DMA_SECCTL2		*(volatile int *)0x0184000C	// DMA channel 2 secondary control register
#define DMA_SRC2		*(volatile int *)0x01840014	// DMA channel 2 source address
#define DMA_DST2		*(volatile int *)0x0184001C	// DMA channel 2 destination address
#define DMA_XFRCNT2		*(volatile int *)0x01840024	// DMA channel 2 transfer counter
#define DMA_PRICTL3		*(volatile int *)0x01840044	// DMA channel 3 priority control register
#define DMA_SECCTL3		*(volatile int *)0x0184004C	// DMA channel 3 secondary control register
#define DMA_SRC3		*(volatile int *)0x01840054	// DMA channel 3 source address
#define DMA_DST3		*(volatile int *)0x0184005C	// DMA channel 3 destination address
#define DMA_XFRCNT3		*(volatile int *)0x01840064	// DMA channel 3 transfer counter
#define	DMA_AUXCTL		*(volatile int *)0x01840070	// DMA auxiliary control register
#define	DMA_GBLADDRA	*(volatile int *)0x01840038	// DMA global address register A
#define	DMA_GBLADDRB	*(volatile int *)0x0184003C	// DMA global address register B
#define	DMA_GBLADDRC	*(volatile int *)0x01840068	// DMA global address register C
#define	DMA_GBLADDRD	*(volatile int *)0x0184006C	// DMA global address register D
#define	DMA_GBLCNTA		*(volatile int *)0x01840028	// DMA global count reload register A
#define	DMA_GBLCNTB		*(volatile int *)0x0184002C	// DMA global count reload register B
#define	DMA_GBLIDXA		*(volatile int *)0x01840030	// DMA global index register A
#define	DMA_GBLIDXB		*(volatile int *)0x01840034	// DMA global index register B
#endif

/* EDMA Registers */
#define PaRAM_OPT	0	// Options
#define PaRAM_SRC	1	// Source Address
#define PaRAM_CNT	2	// Frame count, Element count
#define PaRAM_DST	3	// Destination Address
#define PaRAM_IDX	4	// Frame index, Element index
#define PaRAM_RDL	5	// Element count reload, Link address

#ifdef _C6711_
#define	EDMA_PQSR	*(volatile int *)0x01A0FFE0	// EDMA Priority queue status register
#define	EDMA_CIPR	*(volatile int *)0x01A0FFE4	// EDMA Channel interrupt pending register
#define	EDMA_CIER	*(volatile int *)0x01A0FFE8	// EDMA Channel interrupt enable register
#define	EDMA_CCER	*(volatile int *)0x01A0FFEC	// EDMA Channel chain enable register
#define	EDMA_ER		*(volatile int *)0x01A0FFF0	// EDMA Event register
#define	EDMA_EER	*(volatile int *)0x01A0FFF4	// EDMA Event enable register
#define	EDMA_ECR	*(volatile int *)0x01A0FFF8	// EDMA Event clear register
#define	EDMA_ESR	*(volatile int *)0x01A0FFFC	// EDMA Event set register
#endif

#ifdef _C6713_
#define	EDMA_PQSR	*(volatile int *)0x01A0FFE0	// EDMA Priority queue status register
#define	EDMA_CIPR	*(volatile int *)0x01A0FFE4	// EDMA Channel interrupt pending register 
#define	EDMA_CIER	*(volatile int *)0x01A0FFE8	// EDMA Channel interrupt enable register
#define	EDMA_CCER	*(volatile int *)0x01A0FFEC	// EDMA Channel chain enable register
#define	EDMA_ER		*(volatile int *)0x01A0FFF0	// EDMA Event register
#define	EDMA_EER	*(volatile int *)0x01A0FFF4	// EDMA Event enable register
#define	EDMA_ECR	*(volatile int *)0x01A0FFF8	// EDMA Event clear register
#define	EDMA_ESR	*(volatile int *)0x01A0FFFC	// EDMA Event set register
#endif

#ifdef _C6416_
#define	EDMA_EPRL	*(volatile int *)0x01A0FFDC	// EDMA Polarity low register
#define	EDMA_EPRH	*(volatile int *)0x01A0FF9C	// EDMA Polarity high register
#define	EDMA_PQAR0	*(volatile int *)0x01A0FFC0	// EDMA Priority queue allocation register 0
#define	EDMA_PQAR1	*(volatile int *)0x01A0FFC4	// EDMA Priority queue allocation register 1
#define	EDMA_PQAR2	*(volatile int *)0x01A0FFC8	// EDMA Priority queue allocation register 2
#define	EDMA_PQAR3	*(volatile int *)0x01A0FFCC	// EDMA Priority queue allocation register 3
#define	EDMA_PQSR	*(volatile int *)0x01A0FFE0	// EDMA Priority queue status register
#define	EDMA_CIPRL	*(volatile int *)0x01A0FFE4	// EDMA Channel interrupt pending low register
#define	EDMA_CIPRH	*(volatile int *)0x01A0FFA4	// EDMA Channel interrupt pending high register
#define	EDMA_CIERL	*(volatile int *)0x01A0FFE8	// EDMA Channel interrupt enable low register
#define	EDMA_CIERH	*(volatile int *)0x01A0FFA8	// EDMA Channel interrupt enable high register
#define	EDMA_CCERL	*(volatile int *)0x01A0FFEC	// EDMA Channel chain enable low register
#define	EDMA_CCERH	*(volatile int *)0x01A0FFAC	// EDMA Channel chain enable high register
#define	EDMA_ERL	*(volatile int *)0x01A0FFF0	// EDMA Event low register
#define	EDMA_ERH	*(volatile int *)0x01A0FFB0	// EDMA Event high register
#define	EDMA_EERL	*(volatile int *)0x01A0FFF4	// EDMA Event enable low register
#define	EDMA_EERH	*(volatile int *)0x01A0FFB4	// EDMA Event enable high register
#define	EDMA_ECRL	*(volatile int *)0x01A0FFF8	// EDMA Event clear low register
#define	EDMA_ECRH	*(volatile int *)0x01A0FFB8	// EDMA Event clear high register
#define	EDMA_ESRL	*(volatile int *)0x01A0FFFC	// EDMA Event set low register
#define	EDMA_ESRH	*(volatile int *)0x01A0FFBC	// EDMA Event set high register
#endif

/*	DMA Channel Synchronization Events	*/
#ifdef _C6701_
#define	XEVT0		0xc		// McBSP 0 transmit interrupt
#define	REVT0		0xd		// McBSP 0 receive interrupt
#define	XEVT1		0xe		// McBSP 1 transmit interrupt
#define	REVT1		0xf		// McBSP 1 receive interrupt
#endif

#ifdef _C6203_
#define	XEVT0		0xc		// McBSP 0 transmit interrupt
#define	REVT0		0xd		// McBSP 0 receive interrupt
#define	XEVT1		0xe		// McBSP 1 transmit interrupt
#define	REVT1		0xf		// McBSP 1 receive interrupt
#define	XEVT2		0x11	// McBSP 2 transmit interrupt
#define	REVT2		0x12	// McBSP 2 receive interrupt
#endif
/*	EDMA Channel Synchronization Events	*/
#ifdef _C6711_
#define	XEVT0		0xc		// McBSP 0 transmit interrupt
#define	REVT0		0xd		// McBSP 0 receive interrupt
#define	XEVT1		0xe		// McBSP 1 transmit interrupt
#define	REVT1		0xf		// McBSP 1 receive interrupt
#endif

#ifdef _C6713_
#define	XEVT0		0xc		// McBSP 0 transmit interrupt
#define	REVT0		0xd		// McBSP 0 receive interrupt
#define	XEVT1		0xe		// McBSP 1 transmit interrupt
#define	REVT1		0xf		// McBSP 1 receive interrupt
#endif

#ifdef _C6416_
#define GPEVT0		0x8		// GPIO event 0
#define GPEVT1		0x9		// GPIO event 1
#define GPEVT2		0xa		// GPIO event 2
#define GPEVT3		0xb		// GPIO event 3
#define	XEVT0		0xc		// McBSP 0 transmit interrupt
#define	REVT0		0xd		// McBSP 0 receive interrupt
#define	XEVT1		0xe		// McBSP 1 transmit interrupt
#define	REVT1		0xf		// McBSP 1 receive interrupt
#define	XEVT2		0x11	// McBSP 2 transmit interrupt
#define	REVT2		0x12	// McBSP 2 receive interrupt
#define PCI			0x15	// PCI wakeup interrupt
#define UREVT		0x20	// Utopia receive event
#define UXEVT		0x28	// Utopia transmit event
#define GPEVT8		0x30	// GPIO event 8
#define GPEVT9		0x31	// GPIO event 9
#define GPEVT10		0x32	// GPIO event 10
#define GPEVT11		0x33	// GPIO event 11
#define GPEVT12		0x34	// GPIO event 12
#define GPEVT13		0x35	// GPIO event 13
#define GPEVT14		0x36	// GPIO event 14
#define GPEVT15		0x37	// GPIO event 15
#endif

/*	QDMA Registers	*/
#ifdef	_C6711_
#define	QDMA_OPT	*(volatile int *)0x02000000	// QDMA Options
#define	QDMA_SRC	*(volatile int *)0x02000004	// Source address
#define	QDMA_CNT	*(volatile int *)0x02000008	// Array/frame, Element count
#define	QDMA_DST	*(volatile int *)0x0200000c // Destinaton address
#define	QDMA_IDX	*(volatile int *)0x02000010 // Array/frame, Element index
#define	QDMA_S_OPT	*(volatile int *)0x02000020	// QDMA Options
#define	QDMA_S_SRC	*(volatile int *)0x02000024	// Source address
#define	QDMA_S_CNT	*(volatile int *)0x02000028	// Array/frame, Element count
#define	QDMA_S_DST	*(volatile int *)0x0200002c // Destinaton address
#define	QDMA_S_IDX	*(volatile int *)0x02000030 // Array/frame, Element index
#endif

#ifdef	_C6713_
#define	QDMA_OPT	*(volatile int *)0x02000000
#define	QDMA_SRC	*(volatile int *)0x02000004
#define	QDMA_CNT	*(volatile int *)0x02000008
#define	QDMA_DST	*(volatile int *)0x0200000c
#define	QDMA_IDX	*(volatile int *)0x02000010
#define	QDMA_S_OPT	*(volatile int *)0x02000020
#define	QDMA_S_SRC	*(volatile int *)0x02000024
#define	QDMA_S_CNT	*(volatile int *)0x02000028
#define	QDMA_S_DST	*(volatile int *)0x0200002c
#define	QDMA_S_IDX	*(volatile int *)0x02000030
#endif

#ifdef	_C6416_
#define	QDMA_OPT	*(volatile int *)0x02000000
#define	QDMA_SRC	*(volatile int *)0x02000004
#define	QDMA_CNT	*(volatile int *)0x02000008
#define	QDMA_DST	*(volatile int *)0x0200000c
#define	QDMA_IDX	*(volatile int *)0x02000010
#define	QDMA_S_OPT	*(volatile int *)0x02000020
#define	QDMA_S_SRC	*(volatile int *)0x02000024
#define	QDMA_S_CNT	*(volatile int *)0x02000028
#define	QDMA_S_DST	*(volatile int *)0x0200002c
#define	QDMA_S_IDX	*(volatile int *)0x02000030
#endif

#endif	//_C6000_