c6000.h

ND-Tech DSP 6713 Motor Control Source

#ifndef	_C6000_
#define _C6000_

#ifdef _C6701_
#define	CE0BASE		0x00400000	// CE0BASE Address register
#define	CE1BASE		0x01400000	// CE1BASE Address register
#define	CE2BASE		0x02000000	// CE2BASE Address register
#define	CE3BASE		0x03000000	// CE3BASE Address register
#endif

#ifdef _C6203_
#define	CE0BASE		0x00400000	// CE0BASE Address register
#define	CE1BASE		0x01400000	// CE1BASE Address register
#define	CE2BASE		0x02000000	// CE2BASE Address register
#define	CE3BASE		0x03000000	// CE3BASE Address register
#endif

#ifdef _C6711_
#define	CE0BASE		0x80000000	// CE0BASE Address register
#define	CE1BASE		0x90000000	// CE1BASE Address register
#define	CE2BASE		0xA0000000	// CE2BASE Address register
#define	CE3BASE		0xB0000000	// CE3BASE Address register
#endif

#ifdef _C6713_
#define	CE0BASE		0x80000000	// CE0BASE Address register
#define	CE1BASE		0x90000000	// CE1BASE Address register
#define	CE2BASE		0xA0000000	// CE2BASE Address register
#define	CE3BASE		0xB0000000	// CE3BASE Address register
#endif

#ifdef	_C6416_
#define	ACE0BASE	0x80000000	// ACE0BASE Address register
#define	ACE1BASE	0x90000000	// ACE1BASE Address register
#define	ACE2BASE	0xA0000000	// ACE2BASE Address register
#define	ACE3BASE	0xB0000000	// ACE3BASE Address register
#define	BCE0BASE	0x60000000	// BCE0BASE Address register
#define	BCE1BASE	0x64000000	// BCE1BASE Address register
#define	BCE2BASE	0x68000000	// BCE2BASE Address register
#define	BCE3BASE	0x6C000000	// BCE3BASE Address register
#endif

/* Phase Locked Loop Registers */
#define PLLCSR	 	*(volatile int *)0x01B7C100	// PLL Control/Status Register
#define PLLM	 	*(volatile int *)0x01B7C110	// PLL Multiplier control register
#define	PLLDIV0	 	*(volatile int *)0x01B7C114	// PLL Wrapper Divider 0 register
#define	PLLDIV1	 	*(volatile int *)0x01B7C118	// PLL Wrapper Divider 1 register
#define	PLLDIV2	 	*(volatile int *)0x01B7C11C	// PLL Wrapper Divider 2 register
#define	PLLDIV3	 	*(volatile int *)0x01B7C120	// PLL Wrapper Divider 3 register

/*  McBSP Registers & Address Map   */
#define DRR0     	*(volatile int *)0x018C0000	// Data Receive Register 0
#define DXR0     	*(volatile int *)0x018C0004	// Data Transmit Register 0
#define SPCR0    	*(volatile int *)0x018C0008	// Serial Port Control Register 0
#define RCR0     	*(volatile int *)0x018C000C	// Receive Control Register 0
#define XCR0     	*(volatile int *)0x018C0010	// Transmit Control Register 0
#define SRGR0    	*(volatile int *)0x018C0014	// Sample Rate Generator Register 0
#define MCR0     	*(volatile int *)0x018C0018	// Multichannel Control Register 0
#define RCER0    	*(volatile int *)0x018C001C	// Receive Channel Enable Register 0
#define XCER0    	*(volatile int *)0x018C0020	// Transmit Channel Enable Register 0
#define PCR0     	*(volatile int *)0x018C0024	// Pin Control Register 0

#define DRR1     	*(volatile int *)0x01900000	// Data Receive Register 1
#define DXR1     	*(volatile int *)0x01900004	// Data Transmit Register 1
#define SPCR1    	*(volatile int *)0x01900008	// Serial Port Control Register 1
#define RCR1     	*(volatile int *)0x0190000C	// Receive Control Register 1
#define XCR1     	*(volatile int *)0x01900010	// Transmit Control Register 1
#define SRGR1    	*(volatile int *)0x01900014	// Sample Rate Generator Register 1
#define MCR1     	*(volatile int *)0x01900018	// Multichannel Control Register 1
#define RCER1    	*(volatile int *)0x0190001C	// Receive Channel Enable Register 1
#define XCER1    	*(volatile int *)0x01900020	// Transmit Channel Enable Register 1
#define PCR1     	*(volatile int *)0x01900024	// Pin Control Register 1

#ifdef _C6203_
#define DRR2     	*(volatile int *)0x01A40000
#define DXR2     	*(volatile int *)0x01A40004
#define SPCR2    	*(volatile int *)0x01A40008
#define RCR2     	*(volatile int *)0x01A4000C
#define XCR2     	*(volatile int *)0x01A40010
#define SRGR2    	*(volatile int *)0x01A40014
#define MCR2     	*(volatile int *)0x01A40018
#define RCER2    	*(volatile int *)0x01A4001C
#define XCER2    	*(volatile int *)0x01A40020
#define PCR2     	*(volatile int *)0x01A40024
#endif

#ifdef _C6416_
#define DRR2     	*(volatile int *)0x01A40000
#define DXR2     	*(volatile int *)0x01A40004
#define SPCR2    	*(volatile int *)0x01A40008
#define RCR2     	*(volatile int *)0x01A4000C
#define XCR2     	*(volatile int *)0x01A40010
#define SRGR2    	*(volatile int *)0x01A40014
#define MCR2     	*(volatile int *)0x01A40018
#define RCER2    	*(volatile int *)0x01A4001C
#define XCER2    	*(volatile int *)0x01A40020
#define PCR2     	*(volatile int *)0x01A40024
#endif

/*	EMIF Registers	*/
#ifdef _C6416_
#define ACE1CTL 	*(volatile int *)0x01800004	// EMIF ACE1 space control register
#define ACE0CTL 	*(volatile int *)0x01800008	// EMIF ACE0 space control register
#define ACE2CTL 	*(volatile int *)0x01800010	// EMIF ACE2 space control register
#define ACE3CTL 	*(volatile int *)0x01800014	// EMIF ACE3 space control register
#define ASDCTL		*(volatile int *)0x01800018	// EMIF ASDRAM control register
#define ASDTIM		*(volatile int *)0x0180001C	// EMIF ASDRAM timing register
#define BCE1CTL 	*(volatile int *)0x01A80004	// EMIF BCE1 space control register
#define BCE0CTL 	*(volatile int *)0x01A80008	// EMIF BCE0 space control register
#define BCE2CTL 	*(volatile int *)0x01A80010	// EMIF BCE2 space control register
#define BCE3CTL 	*(volatile int *)0x01A80014	// EMIF BCE3 space control register
#define BSDCTL		*(volatile int *)0x01A80018	// EMIF BSDRAM control register
#else
#define CE1CTL 		*(volatile int *)0x01800004	// EMIF CE1 space control register
#define CE0CTL 		*(volatile int *)0x01800008	// EMIF CE0 space control register
#define CE2CTL	 	*(volatile int *)0x01800010	// EMIF CE2 space control register
#define CE3CTL	 	*(volatile int *)0x01800014	// EMIF CE3 space control register
#define SDCTL		*(volatile int *)0x01800018	// EMIF SDRAM control register
#define SDTIM		*(volatile int *)0x0180001C	// EMIF SDRAM timing register
#endif

/*	Timer Registers	*/
#define	CTL0		*(volatile int *)0x01940000	// Timer 0 control register
#define	PRD0		*(volatile int *)0x01940004	// Timer 0 period register
#define	CNT0		*(volatile int *)0x01940008	// Timer 0 counter register
#define	CTL1		*(volatile int *)0x01980000	// Timer 1 control register
#define	PRD1		*(volatile int *)0x01980004	// Timer 1 period register
#define	CNT1		*(volatile int *)0x01980008	// Timer 1 counter register
#ifdef _C6416_
#define	CTL2		*(volatile int *)0x01AC0000	// Timer 2 control register
#define	PRD2		*(volatile int *)0x01AC0004	// Timer 2 period register
#define	CNT2		*(volatile int *)0x01AC0008	// Timer 2 counter register
#endif

/*	Interrupt Selector Registers	*/
#define MUXH	 	*(volatile int *)0x019c0000	// Interrupt multiplexer high register
#define MUXL	 	*(volatile int *)0x019c0004	// Interrupt multiplexer low register
#define	EXTPOL		*(volatile int *)0x019c0008	// External interrupt polarity register

#define INT4		0
#define INT5		5
#define INT6		10
#define INT7		16
#define INT8		21
#define INT9		26
#define INT10		32
#define INT11		37
#define INT12		42
#define INT13		48
#define INT14		53
#define INT15		58

/*	Available Interrupt	Source	*/
#ifdef _C6701_
#define	DSPINT		0x0		// Host processor to DSP interrupt
#define	TINT0		0x1		// Timer 0 interrupt
#define	TINT1		0x2		// Timer 1 interrupt
#define	SD_INT		0x3		// EMIF SDRAM timer interrupt
#define EXT_INT4	0x4		// External interrupt pin 4
#define EXT_INT5	0x5		// External interrupt pin 5
#define EXT_INT6	0x6		// External interrupt pin 6
#define EXT_INT7	0x7		// External interrupt pin 7
#define DMA_INT0	0x8		// DMA channel 0 interrupt
#define DMA_INT1	0x9		// DMA channel 1 interrupt
#define DMA_INT2	0xa		// DMA channel 2 interrupt
#define DMA_INT3	0xb		// DMA channel 3 interrupt
#define	XINT0		0xc		// McBSP 0 transmit interrupt
#define	RINT0		0xd		// McBSP 0 receive interrupt
#define	XINT1		0xe		// McBSP 1 transmit interrupt
#define	RINT1		0xf		// McBSP 1 receive interrupt
#endif

#ifdef _C6203_
#define	DSPINT		0x0		// Host processor to DSP interrupt
#define	TINT0		0x1		// Timer 0 interrupt
#define	TINT1		0x2		// Timer 1 interrupt
#define	SD_INT		0x3		// EMIF SDRAM timer interrupt
#define EXT_INT4	0x4		// External interrupt pin 4
#define EXT_INT5	0x5		// External interrupt pin 5
#define EXT_INT6	0x6		// External interrupt pin 6
#define EXT_INT7	0x7		// External interrupt pin 7
#define DMA_INT0	0x8		// DMA channel 0 interrupt
#define DMA_INT1	0x9		// DMA channel 1 interrupt
#define DMA_INT2	0xa		// DMA channel 2 interrupt
#define DMA_INT3	0xb		// DMA channel 3 interrupt
#define	XINT0		0xc		// McBSP 0 transmit interrupt
#define	RINT0		0xd		// McBSP 0 receive interrupt
#define	XINT1		0xe		// McBSP 1 transmit interrupt
#define	RINT1		0xf		// McBSP 1 receive interrupt
#define	XINT2		0x11	// McBSP 2 transmit interrupt
#define	RINT2		0x12	// McBSP 2 receive interrupt
#endif

#ifdef _C6711_
#define	DSPINT		0x0		// Host Processer to DSP interrupt
#define	TINT0		0x1		// Timer 0 interrupt
#define	TINT1		0x2		// Timer 1 interrupt
#define	SD_INT		0x3		// EMIF SDRAM timer interrupt
#define EXT_INT4	0x4		// External interrupt pin 4
#define EXT_INT5	0x5		// External interrupt pin 5
#define EXT_INT6	0x6		// External interrupt pin 6
#define EXT_INT7	0x7		// External interrupt pin 7
#define EDMA_INT	0x8		// EDMA channel (0 through 15) interrupt
#define	XINT0		0xc		// McBSP 0 transmit interrupt
#define	RINT0		0xd		// McBSP 0 receive interrupt
#define	XINT1		0xe		// McBSP 1 transmit interrupt
#define	RINT1		0xf		// McBSP 1 receive interrupt
#endif

#ifdef _C6713_
#define	DSPINT		0x0		// Host Processer to DSP interrupt
#define	TINT0		0x1		// Timer 0 interrupt
#define	TINT1		0x2		// Timer 1 interrupt
#define	SD_INT		0x3		// EMIF SDRAM timer interrupt
#define EXT_INT4	0x4		// External interrupt pin 4
#define EXT_INT5	0x5		// External interrupt pin 5
#define EXT_INT6	0x6		// External interrupt pin 6
#define EXT_INT7	0x7		// External interrupt pin 7
#define EDMA_INT	0x8		// EDMA channel (0 through 15) interrupt
#define	XINT0		0xc		// McBSP 0 transmit interrupt
#define	RINT0		0xd		// McBSP 0 receive interrupt
#define	XINT1		0xe		// McBSP 1 transmit interrupt
#define	RINT1		0xf		// McBSP 1 receive interrupt
#endif

#ifdef _C6416_
#define	DSPINT		0x0		// Host Processer to DSP interrupt
#define	TINT0		0x1		// Timer 0 interrupt
#define	TINT1		0x2		// Timer 1 interrupt
#define	SD_INTA		0x3		// EMIFA SDRAM timer interrupt
#define EXT_INT4	0x4		// GPIO interrupt 4/External interrupt pin 4
#define EXT_INT5	0x5		// GPIO interrupt 5/External interrupt pin 5
#define EXT_INT6	0x6		// GPIO interrupt 6/External interrupt pin 6