w5100.c

Wiznet iRadio Source

/*
@file		w5100.c
*/
//#include "types.h"
//#include "delay.h" // for wait function 

#include "w5100.h"



#ifdef __DEF_IINCHIP_PPP__
   #include "md5.h"
#endif

static u8 I_STATUS[MAX_SOCK_NUM];
static u16 SMASK[MAX_SOCK_NUM]; /**< Variable for Tx buffer MASK in each channel */
static u16 RMASK[MAX_SOCK_NUM]; /**< Variable for Rx buffer MASK in each channel */
static u16 SSIZE[MAX_SOCK_NUM]; /**< Max Tx buffer size by each channel */
static u16 RSIZE[MAX_SOCK_NUM]; /**< Max Rx buffer size by each channel */
static u32 SBUFBASEADDRESS[MAX_SOCK_NUM]; /**< Tx buffer base address by each channel */
static u32 RBUFBASEADDRESS[MAX_SOCK_NUM]; /**< Rx buffer base address by each channel */

void delay(u16 val)
{
  u16 i, j;
  
  for(j=0; j < val; j++) {
	  for(i=0; i<0xFFFF; i++);
  }
}


u8 getISR(u8 s)
{
	return I_STATUS[s];
}

void putISR(u8 s, u8 val)
{
   I_STATUS[s] = val;
}

u16 getIINCHIP_RxMAX(u8 s)
{
   return RSIZE[s];
}
u16 getIINCHIP_TxMAX(u8 s)
{
   return SSIZE[s];
}
u16 getIINCHIP_RxMASK(u8 s)
{
   return RMASK[s];
}
u16 getIINCHIP_TxMASK(u8 s)
{
   return SMASK[s];
}
u32 getIINCHIP_RxBASE(u8 s)
{
   return RBUFBASEADDRESS[s];
}
u32 getIINCHIP_TxBASE(u8 s)
{
   return SBUFBASEADDRESS[s];
}

 /**
@brief	This function writes the data into W5100 registers.
*/
u8 IINCHIP_WRITE(u32 addr,u8 data)
{
// DIRECT MODE I/F
//	IINCHIP_ISR_DISABLE();
	*((vu8*)(addr)) = data;
//	IINCHIP_ISR_ENABLE();
	return 1;
}


/**
@brief	This function reads the value from W5100 registers.
*/
u8 IINCHIP_READ(u32 addr)
{
	u8 data;

// DIRECT MODE I/F
//	IINCHIP_ISR_DISABLE();
	data = *((vu8*)(addr));
//	IINCHIP_ISR_ENABLE();
	return data;
}


/**
@brief	This function writes into W5100 memory(Buffer)
*/ 
u16 wiz_write_buf(u32 addr,u8* buf,u16 len)
{
//	IINCHIP_ISR_DISABLE();
   	memcpy((u8 *)addr, buf, len);
//	IINCHIP_ISR_ENABLE();
	return len;
}


/**
@brief	This function reads into W5100 memory(Buffer)
*/ 
u16 wiz_read_buf(u32 addr, u8* buf,u16 len)
{
//	IINCHIP_ISR_DISABLE();
	memcpy(buf, (u8 *)addr, len);
//	IINCHIP_ISR_ENABLE();
	return len;
}


/**
@brief	Socket interrupt routine
*/ 
/*
static void iinchip_irq(void)
{
#ifdef __DEF_IINCHIP_INT__
	u8 int_val;
	IINCHIP_ISR_DISABLE();
	int_val = IINCHIP_READ(IR);

	if (int_val & IR_CONFLICT)
	{
		printf("IP conflict : %.2x\r\n", int_val);
	}
	if (int_val & IR_UNREACH)
	{
		printf("INT Port Unreachable : %.2x\r\n", int_val);
		printf("UIPR0 : %d.%d.%d.%d\r\n", IINCHIP_READ(UIPR0), IINCHIP_READ(UIPR0+1), IINCHIP_READ(UIPR0+2), IINCHIP_READ(UIPR0+3));
		printf("UPORT0 : %.2x %.2x\r\n", IINCHIP_READ(UPORT0), IINCHIP_READ(UPORT0+1));
	}

	if (int_val & IR_SOCK(0))
	{
		I_STATUS[0] = IINCHIP_READ(Sn_IR(0));
		IINCHIP_WRITE(Sn_IR(0), I_STATUS[0] & 0xf);
	}
	if (int_val & IR_SOCK(1))
	{
		I_STATUS[1] = IINCHIP_READ(Sn_IR(1));
		IINCHIP_WRITE(Sn_IR(1), I_STATUS[1] & 0xf);
	}
	if (int_val & IR_SOCK(2))
	{
		I_STATUS[2] = IINCHIP_READ(Sn_IR(2));
		IINCHIP_WRITE(Sn_IR(2), I_STATUS[2] & 0xf);
	}
	if (int_val & IR_SOCK(3))
	{
		I_STATUS[3] = IINCHIP_READ(Sn_IR(3));
		IINCHIP_WRITE(Sn_IR(3), I_STATUS[3] & 0xf);
	}

	IINCHIP_WRITE(IR, int_val);

	IINCHIP_ISR_ENABLE();
	
#endif
}
*/
	
/**
@brief	This function is for resetting of the iinchip. Initializes the iinchip to work in whether DIRECT or INDIRECT mode
*/ 
void iinchip_init(void)
{
	*((volatile u8*)(MR)) = MR_RST;
}


/**
@brief	This function set the transmit & receive buffer size as per the channels is used

Note for TMSR and RMSR bits are as follows\n
bit 1-0 : memory size of channel #0 \n
bit 3-2 : memory size of channel #1 \n
bit 5-4 : memory size of channel #2 \n
bit 7-6 : memory size of channel #3 \n\n
Maximum memory size for Tx, Rx in the W5100 is 8K Bytes,\n
In the range of 8KBytes, the memory size could be allocated dynamically by each channel.\n
Be attentive to sum of memory size shouldn't exceed 8Kbytes\n
and to data transmission and receiption from non-allocated channel may cause some problems.\n
If the 8KBytes memory is already  assigned to centain channel, \n
other 3 channels couldn't be used, for there's no available memory.\n
If two 4KBytes memory are assigned to two each channels, \n
other 2 channels couldn't be used, for there's no available memory.\n
*/ 
void sysinit(
	u8 tx_size, 	/**< tx_size Tx memory size (00 - 1KByte, 01- 2KBtye, 10 - 4KByte, 11 - 8KByte) */
	u8 rx_size		/**< rx_size Rx memory size (00 - 1KByte, 01- 2KBtye, 10 - 4KByte, 11 - 8KByte) */
	)
{
	s16 i;
	s16 ssum,rsum;

#ifdef __DEF_IINCHIP_DBG__
	printf("sysinit()\r\n"); 
#endif

	ssum = 0;
	rsum = 0;
	
	IINCHIP_WRITE(TMSR,tx_size); /* Set Tx memory size for each channel */
	IINCHIP_WRITE(RMSR,rx_size);	 /* Set Rx memory size for each channel */

	SBUFBASEADDRESS[0] = (u32)(__DEF_IINCHIP_MAP_TXBUF__);		/* Set base address of Tx memory for channel #0 */
	RBUFBASEADDRESS[0] = (u32)(__DEF_IINCHIP_MAP_RXBUF__);		/* Set base address of Rx memory for channel #0 */

#ifdef __DEF_IINCHIP_DBG__
	printf("Channel : SEND MEM SIZE : RECV MEM SIZE\r\n");
#endif

   for (i = 0 ; i < MAX_SOCK_NUM; i++)       // Set the size, masking and base address of Tx & Rx memory by each channel
	{
		SSIZE[i] = (s16)(0);
		RSIZE[i] = (s16)(0);
		if (ssum < 8192)
		{
         switch((tx_size >> i*2) & 0x03)  // Set Tx memory size
			{
			case 0:
				SSIZE[i] = (s16)(1024);
				SMASK[i] = (u16)(0x03FF);
				break;
			case 1:
				SSIZE[i] = (s16)(2048);
				SMASK[i] = (u16)(0x07FF);
				break;
			case 2:
				SSIZE[i] = (s16)(4096);
				SMASK[i] = (u16)(0x0FFF);
				break;
			case 3:
				SSIZE[i] = (s16)(8192);
				SMASK[i] = (u16)(0x1FFF);
				break;
			}
		}
		if (rsum < 8192)
		{
         switch((rx_size >> i*2) & 0x03)     // Set Rx memory size
			{
			case 0:
				RSIZE[i] = (s16)(1024);
				RMASK[i] = (u32)(0x000003FF);
				break;
			case 1:
				RSIZE[i] = (s16)(2048);
				RMASK[i] = (u32)(0x000007FF);
				break;
			case 2:
				RSIZE[i] = (s16)(4096);
				RMASK[i] = (u32)(0x00000FFF);
				break;
			case 3:
				RSIZE[i] = (s16)(8192);
				RMASK[i] = (u32)(0x00001FFF);
				break;
			}
		}
		ssum += SSIZE[i];
		rsum += RSIZE[i];

      if (i != 0)             // Sets base address of Tx and Rx memory for channel #1,#2,#3
		{
			SBUFBASEADDRESS[i] = SBUFBASEADDRESS[i-1] + SSIZE[i-1];
			RBUFBASEADDRESS[i] = RBUFBASEADDRESS[i-1] + RSIZE[i-1];
		}
#ifdef __DEF_IINCHIP_DBG__
		printf("%d : %.4x : %.4x : %.4x : %.4x\r\n", i, (u16)SBUFBASEADDRESS[i], (u16)RBUFBASEADDRESS[i], SSIZE[i], RSIZE[i]);
#endif
	}
}

void setMR(u8 val)
{
   IINCHIP_WRITE(MR,val);
}


/**
@brief	This function sets up gateway IP address.
*/ 
void setGAR(
	u8 * addr	/**< a pointer to a 4 -byte array responsible to set the Gateway IP address. */
	)
{
	IINCHIP_WRITE((GAR0 + 0),addr[0]);
	IINCHIP_WRITE((GAR0 + 1),addr[1]);
	IINCHIP_WRITE((GAR0 + 2),addr[2]);
	IINCHIP_WRITE((GAR0 + 3),addr[3]);
}
void getGWIP(u8 * addr)
{
	addr[0] = IINCHIP_READ((GAR0 + 0));
	addr[1] = IINCHIP_READ((GAR0 + 1));
	addr[2] = IINCHIP_READ((GAR0 + 2));
	addr[3] = IINCHIP_READ((GAR0 + 3));
}


/**
@brief	It sets up SubnetMask address
*/ 
void setSUBR(
	u8 * addr	/**< a pointer to a 4 -byte array responsible to set the SubnetMask address */
	)
{
	IINCHIP_WRITE((SUBR0 + 0),addr[0]);
	IINCHIP_WRITE((SUBR0 + 1),addr[1]);
	IINCHIP_WRITE((SUBR0 + 2),addr[2]);
	IINCHIP_WRITE((SUBR0 + 3),addr[3]);
}


/**
@brief	This function sets up MAC address.
*/ 
void setSHAR(
	u8 * addr	/**< a pointer to a 6 -byte array responsible to set the MAC address. */
	)
{
	IINCHIP_WRITE((SHAR0 + 0),addr[0]);
	IINCHIP_WRITE((SHAR0 + 1),addr[1]);
	IINCHIP_WRITE((SHAR0 + 2),addr[2]);
	IINCHIP_WRITE((SHAR0 + 3),addr[3]);
	IINCHIP_WRITE((SHAR0 + 4),addr[4]);
	IINCHIP_WRITE((SHAR0 + 5),addr[5]);
}


/**
@brief	This function sets up Source IP address.
*/
void setSIPR(
	u8 * addr	/**< a pointer to a 4 -byte array responsible to set the Source IP address. */
	)
{
	IINCHIP_WRITE((SIPR0 + 0),addr[0]);
	IINCHIP_WRITE((SIPR0 + 1),addr[1]);
	IINCHIP_WRITE((SIPR0 + 2),addr[2]);
	IINCHIP_WRITE((SIPR0 + 3),addr[3]);
}


/**
@brief	This function gets Interrupt register in common register.
 */
 /*
u8 getIR( void )
{
   return IINCHIP_READ(IR);
}
*/


/**
@brief	This function sets up Retransmission time.

If there is no response from the peer or delay in response then retransmission 
will be there as per RTR (Retry Time-value Register)setting
*/

void setRTR(u16 timeout)
{
	IINCHIP_WRITE(RTR0,(u8)((timeout & 0xff00) >> 8));
	IINCHIP_WRITE((RTR0 + 1),(u8)(timeout & 0x00ff));
}

	

/**
@brief	This function set the number of Retransmission.

If there is no response from the peer or delay in response then recorded time 
as per RTR & RCR register seeting then time out will occur.
*/
void setRCR(u8 retry)
{
	IINCHIP_WRITE(RCR,retry);
}


/**
@brief	This function set the interrupt mask Enable/Disable appropriate Interrupt. ('1' : interrupt enable)

If any bit in IMR is set as '0' then there is not interrupt signal though the bit is
set in IR register.
*/
void setIMR(u8 mask)
{
	IINCHIP_WRITE(IMR,mask); // must be setted 0x10.
}


/**
@brief	These below functions are used to get the Gateway, SubnetMask
		and Source Hardware Address (MAC Address) and Source IP address
*/
/*
void getGAR(u8 * addr)
{
	addr[0] = IINCHIP_READ(GAR0);
	addr[1] = IINCHIP_READ(GAR0+1);
	addr[2] = IINCHIP_READ(GAR0+2);
	addr[3] = IINCHIP_READ(GAR0+3);
}
void getSUBR(u8 * addr)
{
	addr[0] = IINCHIP_READ(SUBR0);
	addr[1] = IINCHIP_READ(SUBR0+1);
	addr[2] = IINCHIP_READ(SUBR0+2);
	addr[3] = IINCHIP_READ(SUBR0+3);
}
void getSHAR(u8 * addr)
{
	addr[0] = IINCHIP_READ(SHAR0);
	addr[1] = IINCHIP_READ(SHAR0+1);
	addr[2] = IINCHIP_READ(SHAR0+2);
	addr[3] = IINCHIP_READ(SHAR0+3);
	addr[4] = IINCHIP_READ(SHAR0+4);
	addr[5] = IINCHIP_READ(SHAR0+5);
}
void getSIPR(u8 * addr)
{
	addr[0] = IINCHIP_READ(SIPR0);
	addr[1] = IINCHIP_READ(SIPR0+1);
	addr[2] = IINCHIP_READ(SIPR0+2);
	addr[3] = IINCHIP_READ(SIPR0+3);
}
*/

/**
@brief	These below functions are used to get the Destination Hardware Address (MAC Address), Destination IP address and Destination Port.
*/
/*
void getSn_DHAR(u8 s, u8 * addr)
{
	addr[0] = IINCHIP_READ(Sn_DHAR0(s));
	addr[1] = IINCHIP_READ(Sn_DHAR0(s)+1);
	addr[2] = IINCHIP_READ(Sn_DHAR0(s)+2);
	addr[3] = IINCHIP_READ(Sn_DHAR0(s)+3);
	addr[4] = IINCHIP_READ(Sn_DHAR0(s)+4);
	addr[5] = IINCHIP_READ(Sn_DHAR0(s)+5);
}
void setSn_DHAR(u8 s, u8 * addr)
{
	IINCHIP_WRITE((Sn_DHAR0(s) + 0),addr[0]);
	IINCHIP_WRITE((Sn_DHAR0(s) + 1),addr[1]);
	IINCHIP_WRITE((Sn_DHAR0(s) + 2),addr[2]);
	IINCHIP_WRITE((Sn_DHAR0(s) + 3),addr[3]);
	IINCHIP_WRITE((Sn_DHAR0(s) + 4),addr[4]);
	IINCHIP_WRITE((Sn_DHAR0(s) + 5),addr[5]);
}
void getSn_DIPR(u8 s, u8 * addr)
{
	addr[0] = IINCHIP_READ(Sn_DIPR0(s));
	addr[1] = IINCHIP_READ(Sn_DIPR0(s)+1);
	addr[2] = IINCHIP_READ(Sn_DIPR0(s)+2);
	addr[3] = IINCHIP_READ(Sn_DIPR0(s)+3);
}
void setSn_DIPR(u8 s, u8 * addr)
{
	IINCHIP_WRITE((Sn_DIPR0(s) + 0),addr[0]);
	IINCHIP_WRITE((Sn_DIPR0(s) + 1),addr[1]);
	IINCHIP_WRITE((Sn_DIPR0(s) + 2),addr[2]);
	IINCHIP_WRITE((Sn_DIPR0(s) + 3),addr[3]);
}
void getSn_DPORT(u8 s, u8 * addr)
{
	addr[0] = IINCHIP_READ(Sn_DPORT0(s));
	addr[1] = IINCHIP_READ(Sn_DPORT0(s)+1);
}
void setSn_DPORT(u8 s, u8 * addr)
{
	IINCHIP_WRITE((Sn_DPORT0(s) + 0),addr[0]);
	IINCHIP_WRITE((Sn_DPORT0(s) + 1),addr[1]);
}
*/

/**
@brief	This sets the maximum segment size of TCP in Active Mode), while in Passive Mode this is set by peer
*/
/*
void setSn_MSS(u8 s, u16 Sn_MSSR0)
{
	IINCHIP_WRITE(Sn_MSSR0(s),(u8)((Sn_MSSR0 & 0xff00) >> 8));
	IINCHIP_WRITE((Sn_MSSR0(s) + 1),(u8)(Sn_MSSR0 & 0x00ff));
}
*/
	
/*
void setSn_TTL(u8 s, u8 ttl)
{
   IINCHIP_WRITE(Sn_TTL(s), ttl);
}
*/

/**
@brief	These below function is used to setup the Protocol Field of IP Header when
		executing the IP Layer RAW mode.
*/
/*
void setSn_PROTO(u8 s, u8 proto)
{
	IINCHIP_WRITE(Sn_PROTO(s),proto);
}
*/

/**
@brief	get socket interrupt status

These below functions are used to read the Interrupt & Soket Status register
*/