readme

这个是systemc的一个小的程序

This directory contains the version 0.3 release of sysc2ver. This is a
program that will automatically convert a SystemC program to verilog.
I have included examples of both a SystemC and verilog simulation
environment. The model I'm using is where a module (example.h/cpp) is
being developed and simulated in SystemC. The module is then converted
to verilog using the sysc2ver.py tool and then run in the verilog
simulation environment.

The files included in this distribution are:

README - This file.
genverilog_rules.txt - Restrictions on how the SystemC program should be written.
sysc2ver.py - The python program that does the conversion.
main.cpp - The main program file for a SystemC example program.
example.h - Header file for example program that can be converted.
example.cpp - Methods file for example program that can be converted.
vdefs.h - Header file with global definitions.
vdefs.v - Verilog include file with global definitions.
Makefile - Makefile for making SystemC example.
test_fixture.h - Header file for SystemC test fixture example
test_fixture.cpp - Methods file for SystemC test fixture example
test_fixture.v - Verilog file for test fixture example
gtkc - Script to start gtkwave and load SystemC generated vcd file.
gtkc_save - Save file from gtkwave that displays all SystemC generated signals.
gtkv - Script to start gtkwave and load verilog generated vcd file.
gtkv_save - Save file from gtkwave that displays all verilog generated signals.
run - Script file to run iverilog and then run the simulation using vvp.

The example file will run under SystemC. To get SystemC and install it,
go to http://www.systemc.org. To build the example and run it do:

make
example.x

To generate a verilog file from the example file do the following:

sysc2ver.py example

This will produce a file named example.v which is the verilog equivalent of
the SystemC program. I have also included an example of a verilog test fixture
file that will include the example.v file that was generated above and run it
on iverilog. To run the verilog example do:

run

To get iverilog and install it, go to http://www.icarus.com/eda/verilog

To view the waveforms generated by both SystemC and Verilog you can use the 
gtkwave program. To get and install it, go to 
http://www.cs.man.ac.uk/apt/tools/gtkwave/index.html

To do list:
- Expand SystemC example file to include examples of all constructs that are
  converted. This will become the test bench for confirming that sysc2ver does
  the conversions correctly.
- Remove restrictions that are listed in genverilog_rules.txt.
- Improve and enhance documentation.