srl_test.vhd

how to infer a shift register for fpga altera xilinx

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    20:39:23 02/22/2009 
-- Design Name: 
-- Module Name:    srl_test - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
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-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity srl_test is
    generic ( srl_size: positive := 33);
    Port ( clk : in  STD_LOGIC;
           en : in  STD_LOGIC;
           din : in  STD_LOGIC_VECTOR (3 downto 0);
           dout : out  STD_LOGIC_VECTOR (3 downto 0));
end srl_test;

architecture Behavioral of srl_test is

type srl_16x4_array is array(srl_size downto 0) of std_logic_vector(3 downto 0);
signal sreg : srl_16x4_array;

begin

dout <= sreg(srl_size);

srl_proc: process(clk,en)
begin
       if rising_edge(clk) then
		     if (en='1') then
			          sreg <= sreg(srl_size-1 downto 0) & din;
			  end if;			 
       end if;

end process;

end Behavioral;