my_entity.vhd

How to infer a finite state machine for fpga altera xilinx

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

-- IS 
-- entity         my_entity                    is 
-- architecture   my_architecture of my_entity is
-- type           my_type                      is
-- case           my_case                      is

-- END
-- end my_entity;
-- end my_architecture;
-- end case;
-- end if;
-- end process;

--module my_module();
  entity my_entity is 
  generic (mult_size: positive := 64);
  port( clk:   in std_logic;
        rst:   in std_logic;
        mplr:  in signed  ((mult_size-1) downto 0);
        mcnd:  in signed  ((mult_size-1) downto 0);
        acc:   out signed ((2*mult_size-1) downto 0);
        done:  out std_logic);
  end my_entity; 


architecture my_architecture of my_entity is

component my_component 
generic ( array_size: positive := 2);
port(   clk:   in std_logic;
        rst:   in std_logic;
        in_A :  in signed  ((2*mult_size-1) downto 0);
        out_A:  out signed ((2*mult_size-1) downto 0));
end component;        
  

-- parameter s0=0, s1=1, s2=2, s3=3, s4=4, s5=5;
   type state_type is (INIT, ADD, SHIFT);
   signal state     : state_type; 
   signal next_state: state_type;
-- reg [31:0] mcnd_temp
   signal     mcnd_temp: signed ((2*mult_size-1) downto 0);
   signal     acc_temp : signed ((2*mult_size-1) downto 0) := (others =>'0');
-- integer    count =0;    
   signal     count    : integer :=0;
   
   attribute syn_encoding : string;
   attribute syn_encoding of state : signal is "safe,onehot";
   

begin

-- always @(posedge clk or posedge rst)
-- begin
process (clk,rst)
begin
   -- if (!rst)
      if (rst = '0') then
      state <= INIT; 
   -- else 
      elsif rising_edge (clk) then 
      --    case (state)
			case  state is 
	  --    INIT:		
			when  INIT   => state <= ADD;
							count <= 0;
							done <= '0';
						--  acc_temp   <= 0;	
							acc_temp   <= (others => '0');
						--  mcnd_temp [15:0]  <= mcnd;	
							mcnd_temp((mult_size-1) downto 0)  <= mcnd;
						--  mcnd_temp [31:16] <= 0;	
							mcnd_temp((2*mult_size-1) downto mult_size) <= (others => '0');
			when  ADD    => state <= SHIFT;
			                if mplr(count)= '1' then
			                acc_temp <= acc_temp + mcnd_temp;
			                end if;
			when  SHIFT  => 
							if (count = mult_size) then
							state <= INIT;
							done <= '1';
							else
							state <= ADD;
							end if;  
							count <= count +1;
							-- acc <= acc_temp;  
			when  others => state <= INIT; 
			end case;
      
      end if;
      
end process; 
-- end

inst1: my_component 
generic map ( array_size => (2*mult_size))
                                port map(   clk => clk, 
                                rst => rst, 
                                in_A => acc_temp,
                                out_A => acc);



end my_architecture;
-- endmodule