📄 i2s_test.c
字号:
Disp("\nEnd of Record!\n");
}
//////////
// Function Name : I2S_RecSoundUsingDMA
// Function Description :
// This function implements the I2S Record operation using DMA.
// DMA Controller1's Channel0 is used for RXDMA.
// Input : ucPort - I2S port number
// ucMode -
// uRecSize - record size
// Output : NONE
// Version :
void I2S_RecSoundUsingDMA(u8 ucCon, u8 ucMode, u32 uRecSize)
{
u8 ucCODECLK=0;
u8 ucBCLK=0;
u8 ucBLTH=0;
u32 uCODECFS = 0;
u32 uBCLKFS = 0;
g_oaI2SInform[ucCon].uRecCount = 0;
g_oaI2SInform[ucCon].uRecLength = uRecSize;
Disp("\n Root Frequency Sample ( 0:256fs 1:512fs 2:384fs(D) 3:768fs ) = ");
ucCODECLK = GetIntNum();
if (ucCODECLK == 0xff ) ucCODECLK = 2;
uCODECFS = I2S_GetRFS(ucCODECLK);
Disp("\n Bit Frequency Sample (0:32fs 1:48fs(D) 2:16fs 3:24fs) = ");
ucBCLK = GetIntNum();
if (ucBCLK == 0xff ) ucBCLK = 1;
uBCLKFS = I2S_GetBFS(ucBCLK);
Disp("\n BLC (0: 16bit(D) 1:8bit ) = ");
ucBLTH = GetIntNum();
if (ucBLTH == 0xff ) ucBLTH = 0;
Disp("\nuBCLKFS:%d, uCODECFS:%d", uBCLKFS, uCODECFS);
Disp("\nI2S Bit Clock = %4.4f MHz", g_oaI2SInform[ucCon].fI2SCodecCLK*uBCLKFS/uCODECFS/1000000);
Disp("\nI2S Sampling Rate = %4.4f kHz\n", g_oaI2SInform[ucCon].fI2SCodecCLK/uCODECFS/1000);
/*---------- DMA1 Interrupt Handler should be registered in here!! ----------*/
INTC_SetVectAddr(g_oaI2SInform[ucCon].ucDMANum ,ISR_DMARecDone);
INTC_Disable(g_oaI2SInform[ucCon].ucDMANum );
/*------------------------------------------------------------------*/
// rI2SCON : RxDMA
I2S_SetI2STxerMode(ucCon, eI2S_XFER_RX);
// rI2SMOD : RxOnlyMode, I2SRootClk, BitClk, BitLength
I2S_SetInterfaceMode(ucCon, eI2S_XFER_RX, eLEFT_LOW_RIGHT_HIGH, eI2S_DATA_I2S, ucCODECLK, ucBCLK, ucBLTH);
I2S_FlushFIFO(ucCon, eI2S_FLUSH_RX, FLUSH); // rI2SFIC : RxFIFO Flush(7)
I2S_FlushFIFO(ucCon, eI2S_FLUSH_RX, NON_FLUSH); // rI2SFIC : RxFIFO No Flush(7)
// DMA Enable
INTC_Enable(g_oaI2SInform[ucCon].ucDMANum );
if(ucMode == I2S_MODE_RECORD_MICIn)
Disp("\n\nAre you ready to record sound via MIC-In on SMDK6400?");
if(ucMode == I2S_MODE_RECORD_LineIn)
Disp("\n\nAre you ready to record sound via Line-In on SMDK6400?");
Disp("\nPress any key to start record!\n");
Getc();
Disp("Recording...\n");
// DMA1 Initailization
DMAC_InitCh((DMA_UNIT)(g_oaI2SInform[ucCon].ucDMACon) , DMA_A, &oI2SDma);
// Interrupt Clear
DMACH_ClearIntPending(&oI2SDma);
DMACH_ClearErrIntPending(&oI2SDma);
// Channel, LLI_Address, SrcAddr, Src Type, DstAddr, Dst Type, Transfer Width, Transfer Size, OpMode(DEMAND), Src Req, Dst Req, Burst
// Channel Set-up [source increment, dest fixed]
Disp("Buffer Addr : 0x%x\n", (u32)(g_oaI2SInform[ucCon].puRecBuf));
DMACH_Setup(DMA_A, 0x0, I2S_GetRegAddr(ucCon,eI2S_RXD), 1, (u32)(g_oaI2SInform[ucCon].puRecBuf), 0, WORD, g_oaI2SInform[ucCon].uRecLength, DEMAND, (DREQ_SRC)(g_oaI2SInform[ucCon].ucDMARxSrc), MEM, SINGLE, &oI2SDma);
// Enable DMA
DMACH_Start(&oI2SDma);
//IIS Start
I2S_SetActive(ucCon, ACTIVE);
while(!g_oaI2SInform[ucCon].ucRecDone)
{
if(Getc()=='x')
{
break;
}
}
g_oaI2SInform[ucCon].ucRecDone = 0;
// I2S Rx Stop !!
I2S_SetActive(ucCon, INACTIVE);
// Stop DMA
DMACH_Stop(&oI2SDma);
I2S_FlushFIFO(ucCon, eI2S_FLUSH_RX, FLUSH);
I2S_FlushFIFO(ucCon, eI2S_FLUSH_RX, NON_FLUSH);
// DMA1 Disable
INTC_Disable(g_oaI2SInform[ucCon].ucDMANum);
Disp("\nEnd of Record!\n");
}
/*---------------------------------- APIs of WM8753 ---------------------------------*/
//////////
// Function Name : I2S_Init8753Driver
// Function Description :
// This function prepares the initialization of WM8753 Driver.
// Input :
// ucMode - I2S Operation Mode
// ucStatus -I2S Operation Status
// Output : NONE
// Version :
void I2S_Init8753Driver(u8 ucPort, u8 ucMode, u8 ucStatus, eI2S_CODEC_MODE eCodecMode)
{
s32 sNum;
Disp("WM8753 Test Start!\n");
/****** PLAY ******/
if(ucMode == I2S_MODE_PLAY)
{
/*PLAY*/
Disp("Select speaker or headphone\n");
Disp("0: receiver, 1: speaker, 2: headphone(D)\n");
sNum = GetIntNum();
/*Default setting value*/
I2S_WrWM8753(ucPort, CHIP_ID, 0x1f, 0x00); // R31 reset
I2S_WrWM8753(ucPort, CHIP_ID, 0x01, 0x00); // R1 DAC control
I2S_WrWM8753(ucPort, CHIP_ID, 0x02, 0x00); // R2 ADC control
I2S_WrWM8753(ucPort, CHIP_ID, 0x03, 0x0a); // R3 PCM Audio interface
// I2S Master Mode ( Codec Slave Mode)
if ( eCodecMode == eI2S_CODEC_SLAVE_MODE )
{
I2S_WrWM8753(ucPort, CHIP_ID, 0x04, 0x02); // R4 HiFI Audio interface 16bit, Codec is Slave
I2S_WrWM8753(ucPort, CHIP_ID, 0x05, 0x33); // R5
I2S_WrWM8753(ucPort, CHIP_ID, 0x06, 0x38); // R6 SR[5:1] 44.1Khz used recording
I2S_WrWM8753(ucPort, CHIP_ID, 0x07, 0xa7); // R7
}
// I2S Slave Mode ( Codec Master Mode)
else if ( eCodecMode == eI2S_CODEC_MASTER_MODE)
{
I2S_WrWM8753(ucPort, CHIP_ID, 0x04, 0x52); // R4 HiFI Audio interface 16bit , Codec is Master
I2S_WrWM8753(ucPort, CHIP_ID, 0x05, 0x33); // R5
I2S_WrWM8753(ucPort, CHIP_ID, 0x06, 0x22); // R6 SR[5:1] Normal mode, 44.1Khz used recording
I2S_WrWM8753(ucPort, CHIP_ID, 0x07, 0x87); // R7
}
I2S_WrWM8753(ucPort, CHIP_ID, 0x08, 0x1ff); // R8
I2S_WrWM8753(ucPort, CHIP_ID, 0x09, 0x1ff); // R9
I2S_WrWM8753(ucPort, CHIP_ID, 0x0a, 0x0f); // R10
I2S_WrWM8753(ucPort, CHIP_ID, 0x0b, 0x0f); // R11
I2S_WrWM8753(ucPort, CHIP_ID, 0x0c, 0x7b); // R12
// I2S_WrWM8753(ucPort, CHIP_ID, 0x0d, 0x00); // R13 ALCSR[7:4] 00 48Khz used playing
I2S_WrWM8753(ucPort, CHIP_ID, 0x0d, 0x22); // R13 ALCSR[7:4] 22 44.1Khz used playing
I2S_WrWM8753(ucPort, CHIP_ID, 0x0e, 0x32); // R14
I2S_WrWM8753(ucPort, CHIP_ID, 0x0f, 0x00); // R15
I2S_WrWM8753(ucPort, CHIP_ID, 0x10, 0xc3); // R16
I2S_WrWM8753(ucPort, CHIP_ID, 0x11, 0xc3); // R17
I2S_WrWM8753(ucPort, CHIP_ID, 0x12, 0xc0); // R18
I2S_WrWM8753(ucPort, CHIP_ID, 0x13, 0x00); // R19
I2S_WrWM8753(ucPort, CHIP_ID, 0x14, 0xcc); // R20 Pwr mgt
I2S_WrWM8753(ucPort, CHIP_ID, 0x15, 0x00); // R21
I2S_WrWM8753(ucPort, CHIP_ID, 0x17, 0x03); // R23 Pwr mgt
I2S_WrWM8753(ucPort, CHIP_ID, 0x18, 0x00); // R24
I2S_WrWM8753(ucPort, CHIP_ID, 0x19, 0x00); // R25
I2S_WrWM8753(ucPort, CHIP_ID, 0x1a, 0x00); // R26
I2S_WrWM8753(ucPort, CHIP_ID, 0x1b, 0x00); // R27
I2S_WrWM8753(ucPort, CHIP_ID, 0x1c, 0x00); // R28
I2S_WrWM8753(ucPort, CHIP_ID, 0x20, 0x55); // R32
I2S_WrWM8753(ucPort, CHIP_ID, 0x21, 0x05); // R33
I2S_WrWM8753(ucPort, CHIP_ID, 0x22, 0x150); // R34 LoutMix.. Must be 0x45(not 0x44)
I2S_WrWM8753(ucPort, CHIP_ID, 0x23, 0x55); // R35
I2S_WrWM8753(ucPort, CHIP_ID, 0x24, 0x150); // R36 RoutMix.. Must be 0x49(not 0x48)
I2S_WrWM8753(ucPort, CHIP_ID, 0x25, 0x55); // R37
I2S_WrWM8753(ucPort, CHIP_ID, 0x26, 0x50); // R38
I2S_WrWM8753(ucPort, CHIP_ID, 0x27, 0x55); // R39
I2S_WrWM8753(ucPort, CHIP_ID, 0x28, 0x15f); // R40(0x51) Lout1 volume Must be 0x51(not 0x50)
I2S_WrWM8753(ucPort, CHIP_ID, 0x29, 0x15f); // R41(0x53) Rout1 volume Must be 0x53(not 0x52)
I2S_WrWM8753(ucPort, CHIP_ID, 0x2a, 0x15f); // R42(0x55) Lout2 volume Must be 0x55(not 0x54)
I2S_WrWM8753(ucPort, CHIP_ID, 0x2b, 0x15f); // R43(0x57) Rout2 volume Must be 0x57(not 0x56)
I2S_WrWM8753(ucPort, CHIP_ID, 0x2c, 0x79); // R44
I2S_WrWM8753(ucPort, CHIP_ID, 0x2d, 0x04); // R45
I2S_WrWM8753(ucPort, CHIP_ID, 0x2e, 0x00); // R46
I2S_WrWM8753(ucPort, CHIP_ID, 0x2f, 0x00); // R47
I2S_WrWM8753(ucPort, CHIP_ID, 0x30, 0x00); // R48
I2S_WrWM8753(ucPort, CHIP_ID, 0x31, 0x97); // R49
I2S_WrWM8753(ucPort, CHIP_ID, 0x32, 0x97); // R50
I2S_WrWM8753(ucPort, CHIP_ID, 0x33, 0x00); // R51
I2S_WrWM8753(ucPort, CHIP_ID, 0x34, 0x04); // R52
I2S_WrWM8753(ucPort, CHIP_ID, 0x35, 0x00); // R53
I2S_WrWM8753(ucPort, CHIP_ID, 0x36, 0x83); // R54
I2S_WrWM8753(ucPort, CHIP_ID, 0x37, 0x24); // R55
I2S_WrWM8753(ucPort, CHIP_ID, 0x38, 0x1ba); // R56
I2S_WrWM8753(ucPort, CHIP_ID, 0x39, 0x00); // R57
I2S_WrWM8753(ucPort, CHIP_ID, 0x3a, 0x83); // R58
I2S_WrWM8753(ucPort, CHIP_ID, 0x3b, 0x24); // R59
I2S_WrWM8753(ucPort, CHIP_ID, 0x3c, 0x1ba); // R60
I2S_WrWM8753(ucPort, CHIP_ID, 0x3d, 0x00); // R61
I2S_WrWM8753(ucPort, CHIP_ID, 0x3f, 0x00); // R63
switch(sNum)
{
case 0 : /*Receiver amp out*/
I2S_WrWM8753(ucPort, CHIP_ID, 0x16, 0x110); // R22(0x2c) Pwr mgt Lout1, out3 on ==> Receiver OK
break;
case 1 : /*speaker out*/
I2S_WrWM8753(ucPort, CHIP_ID, 0x16, 0x60); // R22(0x2c) Pwr mgt L/Rout2 on ==> speaker OK
break;
case 2 : /*headphone*/
I2S_WrWM8753(ucPort, CHIP_ID, 0x16, 0x180); // R22(0x2c) Pwr mgt Lout1, Rout1 on ==> headphone OK
break;
default :
I2S_WrWM8753(ucPort, CHIP_ID, 0x16, 0x180); // R22(0x2c) Pwr mgt Lout1, Rout1 on ==> headphone OK
break;
}
}
/****** Record ******/
else if(ucMode == I2S_MODE_RECORD_MICIn)
{
/*Record*/
Disp("Select MIC1 or MIC2\n");
Disp("1: MIC1(D), 2: MIC2(externel)\n");
sNum = GetIntNum();
/*Default setting value*/
I2S_WrWM8753(ucPort, CHIP_ID, 0x1f, 0x00); // R31(0x3e) Reset
I2S_WrWM8753(ucPort, CHIP_ID, 0x30, 0x02); // R48(0x60) Input control2
I2S_WrWM8753(ucPort, CHIP_ID, 0x02, 0x00); // R2(0x04)
I2S_WrWM8753(ucPort, CHIP_ID, 0x04, 0x02); // R4(0x08) I2S 16bit
I2S_WrWM8753(ucPort, CHIP_ID, 0x05, 0x0b); // R5(0x0a)
I2S_WrWM8753(ucPort, CHIP_ID, 0x06, 0x00); // R6(0x0c)
I2S_WrWM8753(ucPort, CHIP_ID, 0x0c, 0x187); // R12(0x18)
I2S_WrWM8753(ucPort, CHIP_ID, 0x0d, 0x00); // R13(0x1a)
I2S_WrWM8753(ucPort, CHIP_ID, 0x0e, 0x32); // R14(0x1c)
I2S_WrWM8753(ucPort, CHIP_ID, 0x14, 0xe0); // R20(0x28) VMIDSEL(50Kohm), VREF, MICB enable
I2S_WrWM8753(ucPort, CHIP_ID, 0x15, 0x1ff); // R21(0x2a) all enable
I2S_WrWM8753(ucPort, CHIP_ID, 0x16, 0x1ff); // R22(0x2c)
I2S_WrWM8753(ucPort, CHIP_ID, 0x17, 0x1ff); // R23(0x2e)
I2S_WrWM8753(ucPort, CHIP_ID, 0x2f, 0x1e0); // R47(0x5e)
I2S_WrWM8753(ucPort, CHIP_ID, 0x31, 0x13f); // R49(0x62)
I2S_WrWM8753(ucPort, CHIP_ID, 0x32, 0x13f); // R50(0x64)
I2S_WrWM8753(ucPort, CHIP_ID, 0x10, 0x1c3); // R16(0x20)
I2S_WrWM8753(ucPort, CHIP_ID, 0x11, 0x1c3); // R17(0x22)
switch(sNum)
{
case 1 : /*MIC1 Record*/
I2S_WrWM8753(ucPort, CHIP_ID, 0x33, 0x100); // R51(0x66) MIC1 select
break;
case 2 : /*MIC2 Record*/
I2S_WrWM8753(ucPort, CHIP_ID, 0x33, 0x40); // R51(0x66) MIC2 select
break;
default :
I2S_WrWM8753(ucPort, CHIP_ID, 0x33, 0x100); // R51(0x66) MIC1 select
break;
}
}
else if(ucMode == I2S_MODE_RECORD_LineIn)
{
/*Record*/
/*Default setting value*/
I2S_WrWM8753(ucPort, CHIP_ID, 0x1f, 0x00); // R31(0x3e) Reset
I2S_WrWM8753(ucPort, CHIP_ID, 0x30, 0x08); // R48(0x60) Input control2
I2S_WrWM8753(ucPort, CHIP_ID, 0x02, 0x00); // R2(0x04)
I2S_WrWM8753(ucPort, CHIP_ID, 0x04, 0x02); // R4(0x08) I2S 16bit
I2S_WrWM8753(ucPort, CHIP_ID, 0x05, 0x0b); // R5(0x0a)
I2S_WrWM8753(ucPort, CHIP_ID, 0x06, 0x00); // R6(0x0c)
I2S_WrWM8753(ucPort, CHIP_ID, 0x0c, 0x18b); // R12(0x18)
I2S_WrWM8753(ucPort, CHIP_ID, 0x0d, 0x00); // R13(0x1a)
I2S_WrWM8753(ucPort, CHIP_ID, 0x0e, 0x32); // R14(0x1c)
I2S_WrWM8753(ucPort, CHIP_ID, 0x14, 0xe0); // R20(0x28) Pwr_mgt1 VMIDSEL(50Kohm), VREF, MICB enable
I2S_WrWM8753(ucPort, CHIP_ID, 0x15, 0x1ff); // R21(0x2a) Pwr_mgt2 all enable
I2S_WrWM8753(ucPort, CHIP_ID, 0x16, 0x1ff); // R22(0x2c) Pwr_mgt3
I2S_WrWM8753(ucPort, CHIP_ID, 0x17, 0x1ff); // R23(0x2e) Pwr_mgt4
I2S_WrWM8753(ucPort, CHIP_ID, 0x20, 0x77); // R32
I2S_WrWM8753(ucPort, CHIP_ID, 0x21, 0x00); // R33
I2S_WrWM8753(ucPort, CHIP_ID, 0x2e, 0x05); // R46 ADC input Mode as LINE1 and LINE2
I2S_WrWM8753(ucPort, CHIP_ID, 0x2f, 0x1e0); // R47(0x5e)
I2S_WrWM8753(ucPort, CHIP_ID, 0x31, 0x13f); // R49(0x62)
I2S_WrWM8753(ucPort, CHIP_ID, 0x32, 0x13f); // R50(0x64)
I2S_WrWM8753(ucPort, CHIP_ID, 0x10, 0x1c3); // R16(0x20)
I2S_WrWM8753(ucPort, CHIP_ID, 0x11, 0x1c3); // R17(0x22)
}
}
//////////
// Function Name : I2S_WrWM8753
// Function Description :
// This function implements the write function of WM8753.
// Input : uSlvAddr - Address of Slave mode
// ucRegAddr - Address of Register
// usData - data
//----------------------------------------------
// Command Format of WM8753
//----------------------------------------------
// ADDR[15:9], DATA[8:0]
//----------------------------------------------
// Output : NONE
// Version :
void I2S_WrWM8753(u8 ucPort, u8 ucSlvAddr, u8 ucRegAddr, u16 usData)
{
#if 0
IIC_Write(ucSlvAddr, ucRegAddr, (u8)usData);
#else
u8 ucCommand1 = 0;
u8 ucCommand2 = 0;
ucCommand1 = (ucRegAddr << 1) | (( usData >> 8 ) & 0x1);
ucCommand2 = usData & 0xff;
IIC_Write(ucSlvAddr, ucCommand1, ucCommand2);
#endif
}
//////////
// Function Name : I2S_RdWM8753
// Function Description :
// This function implements the read function of WM8753.
// Input : uSlvAddr - Address of Slave mode
// uRegAddr - Address of Register
// Output : NONE
// Version :
u8 I2S_RdWM8753(u8 ucPort, u32 uSlvAddr,u32 uRegAddr)
{
u8 ucData;
IIC_Read((u8) uSlvAddr, (u8) uRegAddr, &ucData);
return ucData;
}
///////////////////////////////////////////////////////////////////////////////////
//////////////////// I2S Main Test ///////////////////////////
///////////////////////////////////////////////////////////////////////////////////
const testFuncMenu g_aI2STestFunc[] =
{
//I2S Function Test Item
I2S_LoopBackTest, "LoopBack Test from I2S0 to I2S1. ",
I2S_PlayWaveInPolling, "Play Wave File in Polling Mode. ",
I2S_PlayWaveInDMA, "Play Wave File in I2S Master and DMA Mode. ",
I2S_PlayWaveInDMASlave, "Play Wave File in I2S Slave and DMA Mode. ",
I2S_RecordInPolling, "Recording in Polling Mode. ",
I2S_RecordSoundViaLineInPlayIt, "Record Sound via Line-In and Play it. ",
I2S_RecordSoundViaMICInPlayIt, "Record Sound via MIC-In and Play it. ",
// Test_CLKOUT, "Test CLKOUT",
// SYSCT_Clock, "Test SysClock",
0,0
};
void I2S_Test(void)
{
u32 uCountFunc=0;
s32 iSel=0;
Disp("\n\n================== I2S Function Test =====================\n\n");
g_ucI2SPortNum = I2S0;
#if 1
I2S_Init(I2S0);
I2S_Init(I2S1);
while(1)
{
for (uCountFunc=0; (u32)(g_aI2STestFunc[uCountFunc].desc)!=0; uCountFunc++)
Disp("%2d: %s\n", uCountFunc, g_aI2STestFunc[uCountFunc].desc);
Disp("\nSelect the function to test : ");
iSel =GetIntNum();
Disp("\n");
if(iSel == -1)
break;
if (iSel>=0 && iSel<(sizeof(g_aI2STestFunc)/8-1))
(g_aI2STestFunc[iSel].func) ();
}
I2S_ReturnPort(I2S0);
I2S_ReturnPort(I2S1);
#else
TestSFR();
#endif
}
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