📄 pixel-sse2.asm
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;*****************************************************************************;* pixel-sse2.asm: h264 encoder library;*****************************************************************************;* Copyright (C) 2005 x264 project;*;* Authors: Alex Izvorski <aizvorksi@gmail.com>;* Loren Merritt <lorenm@u.washington.edu>;*;* This program is free software; you can redistribute it and/or modify;* it under the terms of the GNU General Public License as published by;* the Free Software Foundation; either version 2 of the License, or;* (at your option) any later version.;*;* This program is distributed in the hope that it will be useful,;* but WITHOUT ANY WARRANTY; without even the implied warranty of;* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the;* GNU General Public License for more details.;*;* You should have received a copy of the GNU General Public License;* along with this program; if not, write to the Free Software;* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111, USA.;*****************************************************************************BITS 64;=============================================================================; Macros and other preprocessor constants;=============================================================================%include "amd64inc.asm"SECTION .rodata align=16pw_1: times 8 dw 1ssim_c1: times 4 dd 416 ; .01*.01*255*255*64ssim_c2: times 4 dd 235963 ; .03*.03*255*255*64*63mask_ff: times 16 db 0xff times 16 db 0SECTION .text%macro HADDD 2 ; sum junk movhlps %2, %1 paddd %1, %2 pshuflw %2, %1, 0xE paddd %1, %2%endmacro%macro HADDW 2 pmaddwd %1, [pw_1 GLOBAL] HADDD %1, %2%endmacro%macro SAD_INC_4x16P_SSE2 0 movdqu xmm1, [rdx] movdqu xmm2, [rdx+rcx] lea rdx, [rdx+2*rcx] movdqu xmm3, [rdx] movdqu xmm4, [rdx+rcx] psadbw xmm1, [rdi] psadbw xmm2, [rdi+rsi] lea rdi, [rdi+2*rsi] psadbw xmm3, [rdi] psadbw xmm4, [rdi+rsi] lea rdi, [rdi+2*rsi] lea rdx, [rdx+2*rcx] paddw xmm1, xmm2 paddw xmm3, xmm4 paddw xmm0, xmm1 paddw xmm0, xmm3%endmacro%macro SAD_END_SSE2 0 movdqa xmm1, xmm0 psrldq xmm0, 8 paddw xmm0, xmm1 movd eax, xmm0 ret%endmacro;-----------------------------------------------------------------------------; int x264_pixel_sad_16x16_sse2 (uint8_t *, int, uint8_t *, int );-----------------------------------------------------------------------------cglobal x264_pixel_sad_16x16_sse2 movdqu xmm0, [rdx] movdqu xmm1, [rdx+rcx] lea rdx, [rdx+2*rcx] movdqu xmm2, [rdx] movdqu xmm3, [rdx+rcx] lea rdx, [rdx+2*rcx] psadbw xmm0, [rdi] psadbw xmm1, [rdi+rsi] lea rdi, [rdi+2*rsi] movdqu xmm4, [rdx] paddw xmm0, xmm1 psadbw xmm2, [rdi] psadbw xmm3, [rdi+rsi] lea rdi, [rdi+2*rsi] movdqu xmm5, [rdx+rcx] lea rdx, [rdx+2*rcx] paddw xmm2, xmm3 movdqu xmm6, [rdx] movdqu xmm7, [rdx+rcx] lea rdx, [rdx+2*rcx] paddw xmm0, xmm2 psadbw xmm4, [rdi] psadbw xmm5, [rdi+rsi] lea rdi, [rdi+2*rsi] movdqu xmm1, [rdx] paddw xmm4, xmm5 psadbw xmm6, [rdi] psadbw xmm7, [rdi+rsi] lea rdi, [rdi+2*rsi] movdqu xmm2, [rdx+rcx] lea rdx, [rdx+2*rcx] paddw xmm6, xmm7 movdqu xmm3, [rdx] paddw xmm0, xmm4 movdqu xmm4, [rdx+rcx] lea rdx, [rdx+2*rcx] paddw xmm0, xmm6 psadbw xmm1, [rdi] psadbw xmm2, [rdi+rsi] lea rdi, [rdi+2*rsi] movdqu xmm5, [rdx] paddw xmm1, xmm2 psadbw xmm3, [rdi] psadbw xmm4, [rdi+rsi] lea rdi, [rdi+2*rsi] movdqu xmm6, [rdx+rcx] lea rdx, [rdx+2*rcx] paddw xmm3, xmm4 movdqu xmm7, [rdx] paddw xmm0, xmm1 movdqu xmm1, [rdx+rcx] paddw xmm0, xmm3 psadbw xmm5, [rdi] psadbw xmm6, [rdi+rsi] lea rdi, [rdi+2*rsi] paddw xmm5, xmm6 psadbw xmm7, [rdi] psadbw xmm1, [rdi+rsi] paddw xmm7, xmm1 paddw xmm0, xmm5 paddw xmm0, xmm7 SAD_END_SSE2;-----------------------------------------------------------------------------; int x264_pixel_sad_16x8_sse2 (uint8_t *, int, uint8_t *, int );-----------------------------------------------------------------------------cglobal x264_pixel_sad_16x8_sse2 pxor xmm0, xmm0 SAD_INC_4x16P_SSE2 SAD_INC_4x16P_SSE2 SAD_END_SSE2%macro SSD_INC_2x16P_SSE2 0 movdqu xmm1, [rdi] movdqu xmm2, [rdx] movdqu xmm3, [rdi+rsi] movdqu xmm4, [rdx+rcx] movdqa xmm5, xmm1 movdqa xmm6, xmm3 psubusb xmm1, xmm2 psubusb xmm3, xmm4 psubusb xmm2, xmm5 psubusb xmm4, xmm6 por xmm1, xmm2 por xmm3, xmm4 movdqa xmm2, xmm1 movdqa xmm4, xmm3 punpcklbw xmm1, xmm7 punpckhbw xmm2, xmm7 punpcklbw xmm3, xmm7 punpckhbw xmm4, xmm7 pmaddwd xmm1, xmm1 pmaddwd xmm2, xmm2 pmaddwd xmm3, xmm3 pmaddwd xmm4, xmm4 lea rdi, [rdi+2*rsi] lea rdx, [rdx+2*rcx] paddd xmm1, xmm2 paddd xmm3, xmm4 paddd xmm0, xmm1 paddd xmm0, xmm3%endmacro%macro SSD_START_SSE2 0 pxor xmm7, xmm7 ; zero pxor xmm0, xmm0 ; mm0 holds the sum%endmacro%macro SSD_END_SSE2 0 HADDD xmm0, xmm1 movd eax, xmm0 ret%endmacro;-----------------------------------------------------------------------------; int x264_pixel_ssd_16x16_sse2 (uint8_t *, int, uint8_t *, int );-----------------------------------------------------------------------------cglobal x264_pixel_ssd_16x16_sse2 SSD_START_SSE2%rep 8 SSD_INC_2x16P_SSE2%endrep SSD_END_SSE2;-----------------------------------------------------------------------------; int x264_pixel_ssd_16x8_sse2 (uint8_t *, int, uint8_t *, int );-----------------------------------------------------------------------------cglobal x264_pixel_ssd_16x8_sse2 SSD_START_SSE2%rep 4 SSD_INC_2x16P_SSE2%endrep SSD_END_SSE2%macro SUMSUB_BADC 4 paddw %1, %2 paddw %3, %4 paddw %2, %2 paddw %4, %4 psubw %2, %1 psubw %4, %3%endmacro%macro HADAMARD1x4 4 SUMSUB_BADC %1, %2, %3, %4 SUMSUB_BADC %1, %3, %2, %4%endmacro%macro HADAMARD1x8 8 SUMSUB_BADC %1, %5, %2, %6 SUMSUB_BADC %3, %7, %4, %8 SUMSUB_BADC %1, %3, %2, %4 SUMSUB_BADC %5, %7, %6, %8 SUMSUB_BADC %1, %2, %3, %4 SUMSUB_BADC %5, %6, %7, %8%endmacro;;; row transform not used, because phaddw is much slower than paddw on a Conroe;%macro PHSUMSUB 3; movdqa %3, %1; phaddw %1, %2; phsubw %3, %2;%endmacro;%macro HADAMARD4x1_SSSE3 5 ; ABCD-T -> ADTC; PHSUMSUB %1, %2, %5; PHSUMSUB %3, %4, %2; PHSUMSUB %1, %3, %4; PHSUMSUB %5, %2, %3;%endmacro%macro SBUTTERFLY 5 mov%1 %5, %3 punpckl%2 %3, %4 punpckh%2 %5, %4%endmacro%macro SBUTTERFLY2 5 ; not really needed, but allows transpose4x4 to not shuffle registers mov%1 %5, %3 punpckh%2 %3, %4 punpckl%2 %5, %4%endmacro%macro TRANSPOSE4x4D 5 ; ABCD-T -> ADTC SBUTTERFLY dqa, dq, %1, %2, %5 SBUTTERFLY dqa, dq, %3, %4, %2 SBUTTERFLY dqa, qdq, %1, %3, %4 SBUTTERFLY dqa, qdq, %5, %2, %3%endmacro%macro TRANSPOSE2x4x4W 5 ; ABCD-T -> ABCD SBUTTERFLY dqa, wd, %1, %2, %5 SBUTTERFLY dqa, wd, %3, %4, %2 SBUTTERFLY dqa, dq, %1, %3, %4 SBUTTERFLY2 dqa, dq, %5, %2, %3 SBUTTERFLY dqa, qdq, %1, %3, %2 SBUTTERFLY2 dqa, qdq, %4, %5, %3%endmacro%macro TRANSPOSE8x8 9 ; ABCDEFGH-T -> AFHDTECB SBUTTERFLY dqa, wd, %1, %2, %9 SBUTTERFLY dqa, wd, %3, %4, %2 SBUTTERFLY dqa, wd, %5, %6, %4 SBUTTERFLY dqa, wd, %7, %8, %6 SBUTTERFLY dqa, dq, %1, %3, %8 SBUTTERFLY dqa, dq, %9, %2, %3 SBUTTERFLY dqa, dq, %5, %7, %2 SBUTTERFLY dqa, dq, %4, %6, %7 SBUTTERFLY dqa, qdq, %1, %5, %6 SBUTTERFLY dqa, qdq, %9, %4, %5 SBUTTERFLY dqa, qdq, %8, %2, %4 SBUTTERFLY dqa, qdq, %3, %7, %2%endmacro%macro LOAD_DIFF_8P 4 ; MMP, MMT, [pix1], [pix2] movq %1, %3 movq %2, %4 punpcklbw %1, %2 punpcklbw %2, %2 psubw %1, %2%endmacro%macro LOAD_DIFF_4x8P 6 ; 4x dest, 2x temp LOAD_DIFF_8P %1, %5, [parm1q], [parm3q] LOAD_DIFF_8P %2, %6, [parm1q+parm2q], [parm3q+parm4q] LOAD_DIFF_8P %3, %5, [parm1q+2*parm2q], [parm3q+2*parm4q] LOAD_DIFF_8P %4, %6, [parm1q+r10], [parm3q+r11]%endmacro%macro SUM1x8_SSE2 3 ; 01 junk sum pxor %2, %2 psubw %2, %1 pmaxsw %1, %2 paddusw %3, %1%endmacro%macro SUM4x4_SSE2 4 ; 02 13 junk sum pxor %3, %3 psubw %3, %1 pmaxsw %1, %3 pxor %3, %3 psubw %3, %2 pmaxsw %2, %3 paddusw %4, %1 paddusw %4, %2%endmacro%macro SUM8x4_SSE2 7 ; a02 a13 junk1 b02 b13 junk2 (1=4 2=5 3=6) sum pxor %3, %3 pxor %6, %6 psubw %3, %1 psubw %6, %4 pmaxsw %1, %3 pmaxsw %4, %6 pxor %3, %3 pxor %6, %6 psubw %3, %2 psubw %6, %5 pmaxsw %2, %3 pmaxsw %5, %6 paddusw %1, %2 paddusw %4, %5 paddusw %7, %1 paddusw %7, %4%endmacro⌨️ 快捷键说明
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