__projnav.log

来自「通过一个主时钟信号完成异步FIFO读写时钟信号的产生。编译通过实现功能。」· LOG 代码 · 共 307 行

LOG
307 行
字号 
Project Navigator Auto-Make Log File-------------------------------------




Project Navigator Auto-Make Log File-------------------------------------



Project Navigator Auto-Make Log File-------------------------------------




Project Navigator Auto-Make Log File-------------------------------------




Project Navigator Auto-Make Log File-------------------------------------



Project Navigator Auto-Make Log File-------------------------------------



Project Navigator Auto-Make Log File-------------------------------------




Project Navigator Auto-Make Log File-------------------------------------




Project Navigator Auto-Make Log File-------------------------------------




Project Navigator Auto-Make Log File-------------------------------------




Project Navigator Auto-Make Log File-------------------------------------




Project Navigator Auto-Make Log File-------------------------------------




Project Navigator Auto-Make Log File-------------------------------------




Project Navigator Auto-Make Log File-------------------------------------



Project Navigator Auto-Make Log File-------------------------------------



Started process "View RTL Schematic".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling vhdl file "F:/data file/ou/clk/clk.vhd" in Library work.Entity <clkdiv> compiled.Entity <clkdiv> (Architecture <Behavioral>) compiled.=========================================================================*                            HDL Analysis                               *=========================================================================Analyzing Entity <clkdiv> (Architecture <Behavioral>).INFO:Xst:1304 - Contents of register <dagPL_clk_temp1_q> in unit <clkdiv> never changes during circuit operation. The register is replaced by logic.INFO:Xst:1304 - Contents of register <dagPL_clk_temp2_q> in unit <clkdiv> never changes during circuit operation. The register is replaced by logic.Entity <clkdiv> analyzed. Unit <clkdiv> generated.=========================================================================*                           HDL Synthesis                               *=========================================================================Synthesizing Unit <clkdiv>.    Related source file is "F:/data file/ou/clk/clk.vhd".WARNING:Xst:647 - Input <clk_in> is never used.Unit <clkdiv> synthesized.=========================================================================*                       Advanced HDL Synthesis                          *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportFound no macro==================================================================================================================================================*                         Low Level Synthesis                           *==================================================================================================================================================*                            Final Report                               *=========================================================================

Project Navigator Auto-Make Log File-------------------------------------




Project Navigator Auto-Make Log File-------------------------------------




Project Navigator Auto-Make Log File-------------------------------------




Project Navigator Auto-Make Log File-------------------------------------



Project Navigator Auto-Make Log File-------------------------------------




Project Navigator Auto-Make Log File-------------------------------------




Project Navigator Auto-Make Log File-------------------------------------



Project Navigator Auto-Make Log File-------------------------------------




Project Navigator Auto-Make Log File-------------------------------------




Project Navigator Auto-Make Log File-------------------------------------




Project Navigator Auto-Make Log File-------------------------------------




Project Navigator Auto-Make Log File-------------------------------------

__projnav.log - 源码说明

本页面展示了「通过一个主时钟信号完成异步FIFO读写时钟信号的产生。编译通过实现功能。」中的 __projnav.log 源码文件，采用 LOG 编程语言编写，共 307 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

虫虫下载站收录了大量与FIFO相关的技术资源，包括源代码、技术文档、电路图等，是电子工程师和嵌入式开发者的专业学习平台。

⌨️ 快捷键说明

复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?