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📁 通过一个主时钟信号完成异步FIFO读写时钟信号的产生。编译通过实现功能。
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Project Navigator Auto-Make Log File-------------------------------------




Project Navigator Auto-Make Log File-------------------------------------




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Started process "View RTL Schematic".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling vhdl file "F:/data file/ou/clk/clk.vhd" in Library work.Entity <clkdiv> compiled.Entity <clkdiv> (Architecture <Behavioral>) compiled.=========================================================================*                            HDL Analysis                               *=========================================================================Analyzing Entity <clkdiv> (Architecture <Behavioral>).INFO:Xst:1304 - Contents of register <dagPL_clk_temp1_q> in unit <clkdiv> never changes during circuit operation. The register is replaced by logic.INFO:Xst:1304 - Contents of register <dagPL_clk_temp2_q> in unit <clkdiv> never changes during circuit operation. The register is replaced by logic.Entity <clkdiv> analyzed. Unit <clkdiv> generated.=========================================================================*                           HDL Synthesis                               *=========================================================================Synthesizing Unit <clkdiv>.    Related source file is "F:/data file/ou/clk/clk.vhd".WARNING:Xst:647 - Input <clk_in> is never used.Unit <clkdiv> synthesized.=========================================================================*                       Advanced HDL Synthesis                          *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportFound no macro==================================================================================================================================================*                         Low Level Synthesis                           *==================================================================================================================================================*                            Final Report                               *=========================================================================

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