transcript

通过一个主时钟信号完成异步FIFO读写时钟信号的产生。编译通过实现功能。

# Reading D:/Modeltech_6.1f/tcl/vsim/pref.tcl 
# //  ModelSim SE 6.1f May 12 2006 
# //
# //  Copyright 2006 Mentor Graphics Corporation
# //              All Rights Reserved.
# //
# //  THIS WORK CONTAINS TRADE SECRET AND 
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# //  AND IS SUBJECT TO LICENSE TERMS.
# //
# do clk_tb.fdo 
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 6.1f Compiler 2006.05 May 12 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity clkdiv
# -- Compiling architecture behavioral of clkdiv
# Model Technology ModelSim SE vcom 6.1f Compiler 2006.05 May 12 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity clk_tb
# -- Compiling architecture testbench_arch of clk_tb
# vsim -lib work -t 1ps clk_tb 
# Loading d:\Modeltech_6.1f\win32/../std.standard
# Loading d:\Modeltech_6.1f\win32/../ieee.std_logic_1164(body)
# Loading d:\Modeltech_6.1f\win32/../ieee.std_logic_arith(body)
# Loading d:\Modeltech_6.1f\win32/../ieee.std_logic_unsigned(body)
# Loading d:\Modeltech_6.1f\win32/../std.textio(body)
# Loading d:\Modeltech_6.1f\win32/../ieee.std_logic_textio(body)
# Loading work.clk_tb(testbench_arch)
# Loading work.clkdiv(behavioral)
# .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs.pw.wf
# .main_pane.workspace
# .main_pane.signals.interior.cs
# ** Failure: Simulation successful (not a failure).  No problems detected.
#    Time: 2200 ns  Iteration: 0  Process: /clk_tb/line__70 File: clk_tb.vhw
# Break at clk_tb.vhw line 122
# Simulation Breakpoint: Break at clk_tb.vhw line 122
# MACRO ./clk_tb.fdo PAUSED at line 13