clk.vhd

通过一个主时钟信号完成异步FIFO读写时钟信号的产生。编译通过实现功能。

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity clkdiv is
port
(
  clk_in:in std_logic;
  rd_clk:out std_logic;  
  wr_clk:out std_logic
);
end clkdiv;
---------------时钟分频器产生读写时钟信号-----------------------------------------
architecture Behavioral of clkdiv is
  signal dagPL_clk_temp1_q:std_logic:='0';
  signal dagPL_clk_temp2_q:std_logic:='0';
  signal count1:std_logic_vector(2 downto 0):="000";
  signal count2:std_logic_vector(2 downto 0):="000";
begin
rdclk: process(clk_in)
   begin
	if(clk_in'event and clk_in='1')then
	    if(count1 /= 2) then
			   count1 <= count1 + 1;
       else
			   count1 <= (others =>'0');
			   dagPL_clk_temp1_q <= not dagPL_clk_temp1_q;
       end if;
	end if;
  end process;
rd_clk<=dagPL_clk_temp1_q;

wrclk:process(clk_in)
   begin
	if(clk_in'event and clk_in='1')then
		if(count2 /= 1) then
			  count2 <= count2 + 1;
      else
			  count2 <= (others =>'0');
	        dagPL_clk_temp2_q<= not dagPL_clk_temp2_q;
		  end if;
	end if;
  end process;	
wr_clk<=dagPL_clk_temp2_q;
end Behavioral;