clk_tb.ant

通过一个主时钟信号完成异步FIFO读写时钟信号的产生。编译通过实现功能。

--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 7.1.04i
--  \   \         Application : ISE Foundation
--  /   /         Filename : clk_tb.ant
-- /___/   /\     Timestamp : Fri Jan 09 22:35:18 2009
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: 
--Design Name: clk_tb
--Device: Xilinx
--

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY clk_tb IS
END clk_tb;

ARCHITECTURE testbench_arch OF clk_tb IS
    FILE RESULTS: TEXT OPEN WRITE_MODE IS "F:\data file\ou\clk\clk_tb.ano";

    COMPONENT clkdiv
        PORT (
            clk_in : In std_logic;
            rd_clk : Out std_logic;
            wr_clk : Out std_logic
        );
    END COMPONENT;

    SIGNAL clk_in : std_logic := '0';
    SIGNAL rd_clk : std_logic := '0';
    SIGNAL wr_clk : std_logic := '0';

    SHARED VARIABLE TX_ERROR : INTEGER := 0;
    SHARED VARIABLE TX_OUT : LINE;

    constant PERIOD : time := 200 ns;
    constant DUTY_CYCLE : real := 0.5;
    constant OFFSET : time := 0 ns;

    BEGIN
        UUT : clkdiv
        PORT MAP (
            clk_in => clk_in,
            rd_clk => rd_clk,
            wr_clk => wr_clk
        );

        PROCESS    -- clock process for clk_in
        BEGIN
            WAIT for OFFSET;
            CLOCK_LOOP : LOOP
                clk_in <= '0';
                WAIT FOR (PERIOD - (PERIOD * DUTY_CYCLE));
                clk_in <= '1';
                WAIT FOR (PERIOD * DUTY_CYCLE);
            END LOOP CLOCK_LOOP;
        END PROCESS;

        PROCESS    -- Annotation process for clk_in
            VARIABLE TX_TIME : INTEGER := 0;

            PROCEDURE ANNOTATE_rd_clk(
                TX_TIME : INTEGER
            ) IS
                VARIABLE TX_STR : String(1 to 4096);
                VARIABLE TX_LOC : LINE;
            BEGIN
                STD.TEXTIO.write(TX_LOC, string'("Annotate["));
                STD.TEXTIO.write(TX_LOC, TX_TIME);
                STD.TEXTIO.write(TX_LOC, string'(", rd_clk, "));
                IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, rd_clk);
                STD.TEXTIO.write(TX_LOC, string'("]"));
                TX_STR(TX_LOC.all'range) := TX_LOC.all;
                STD.TEXTIO.writeline(RESULTS, TX_LOC);
                STD.TEXTIO.Deallocate(TX_LOC);
            END;
            PROCEDURE ANNOTATE_wr_clk(
                TX_TIME : INTEGER
            ) IS
                VARIABLE TX_STR : String(1 to 4096);
                VARIABLE TX_LOC : LINE;
            BEGIN
                STD.TEXTIO.write(TX_LOC, string'("Annotate["));
                STD.TEXTIO.write(TX_LOC, TX_TIME);
                STD.TEXTIO.write(TX_LOC, string'(", wr_clk, "));
                IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, wr_clk);
                STD.TEXTIO.write(TX_LOC, string'("]"));
                TX_STR(TX_LOC.all'range) := TX_LOC.all;
                STD.TEXTIO.writeline(RESULTS, TX_LOC);
                STD.TEXTIO.Deallocate(TX_LOC);
            END;
        BEGIN
            WAIT for 1 fs;
            ANNOTATE_rd_clk(0);
            ANNOTATE_wr_clk(0);
            WAIT for OFFSET;
            TX_TIME := TX_TIME + 0;
            ANNO_LOOP : LOOP
                --Rising Edge
                WAIT for 115 ns;
                TX_TIME := TX_TIME + 115;
                ANNOTATE_rd_clk(TX_TIME);
                ANNOTATE_wr_clk(TX_TIME);
                WAIT for 85 ns;
                TX_TIME := TX_TIME + 85;
            END LOOP ANNO_LOOP;
        END PROCESS;

        PROCESS
            BEGIN
                WAIT FOR 2200 ns;

                STD.TEXTIO.write(TX_OUT, string'("Total[]"));
                STD.TEXTIO.writeline(RESULTS, TX_OUT);
                ASSERT (FALSE) REPORT
                    "Success! Simulation for annotation completed"
                    SEVERITY FAILURE;
            END PROCESS;

    END testbench_arch;