📄 dm642init.asm
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;******************************************************************************
;* TMS320C6x C/C++ Codegen PC v6.0.8 *
;* Date/Time created: Mon Mar 10 23:01:59 2008 *
;******************************************************************************
.compiler_opts --c64p_l1d_workaround=default --endian=little --hll_source=on --mem_model:code=far --mem_model:data=far --predefine_memory_model_macros --quiet --silicon_version=6400 --symdebug:skeletal
;******************************************************************************
;* GLOBAL FILE PARAMETERS *
;* *
;* Architecture : TMS320C64xx *
;* Optimization : Enabled at level 3 *
;* Optimizing for : Speed *
;* Based on options: -o3, no -ms *
;* Endian : Little *
;* Interrupt Thrshld : Disabled *
;* Data Access Model : Far *
;* Pipelining : Enabled *
;* Speculate Loads : Disabled *
;* Memory Aliases : Presume not aliases (optimistic) *
;* Debug Info : DWARF Debug for Program Analysis w/Optimization *
;* *
;******************************************************************************
.asg A15, FP
.asg B14, DP
.asg B15, SP
.global $bss
$C$DW$CU .dwtag DW_TAG_compile_unit
.dwattr $C$DW$CU, DW_AT_name("dm642init.c")
.dwattr $C$DW$CU, DW_AT_producer("TMS320C6x C/C++ Codegen PC v6.0.8 Copyright (c) 1996-2006 Texas Instruments Incorporated")
.dwattr $C$DW$CU, DW_AT_TI_version(0x01)
;*****************************************************************************
;* CINIT RECORDS *
;*****************************************************************************
.sect ".cinit"
.align 8
.field $C$IR_1,32
.field _LinkStr+0,32
.field $C$SL1,32 ; _LinkStr[0] @ 0
.field $C$SL2,32 ; _LinkStr[1] @ 32
.field $C$SL3,32 ; _LinkStr[2] @ 64
.field $C$SL4,32 ; _LinkStr[3] @ 96
.field $C$SL5,32 ; _LinkStr[4] @ 128
$C$IR_1: .set 20
$C$DW$1 .dwtag DW_TAG_subprogram, DW_AT_name("printf")
.dwattr $C$DW$1, DW_AT_TI_symbol_name("_printf")
.dwattr $C$DW$1, DW_AT_type(*$C$DW$T$10)
.dwattr $C$DW$1, DW_AT_declaration
.dwattr $C$DW$1, DW_AT_external
$C$DW$2 .dwtag DW_TAG_formal_parameter, DW_AT_type(*$C$DW$T$50)
$C$DW$3 .dwtag DW_TAG_unspecified_parameters
.dwendtag $C$DW$1
$C$DW$4 .dwtag DW_TAG_subprogram, DW_AT_name("mmCopy")
.dwattr $C$DW$4, DW_AT_TI_symbol_name("_mmCopy")
.dwattr $C$DW$4, DW_AT_declaration
.dwattr $C$DW$4, DW_AT_external
$C$DW$5 .dwtag DW_TAG_formal_parameter, DW_AT_type(*$C$DW$T$3)
$C$DW$6 .dwtag DW_TAG_formal_parameter, DW_AT_type(*$C$DW$T$3)
$C$DW$7 .dwtag DW_TAG_formal_parameter, DW_AT_type(*$C$DW$T$20)
.dwendtag $C$DW$4
$C$DW$8 .dwtag DW_TAG_subprogram, DW_AT_name("EVMDM642_init")
.dwattr $C$DW$8, DW_AT_TI_symbol_name("_EVMDM642_init")
.dwattr $C$DW$8, DW_AT_declaration
.dwattr $C$DW$8, DW_AT_external
$C$DW$9 .dwtag DW_TAG_subprogram, DW_AT_name("EVMDM642_LED_init")
.dwattr $C$DW$9, DW_AT_TI_symbol_name("_EVMDM642_LED_init")
.dwattr $C$DW$9, DW_AT_declaration
.dwattr $C$DW$9, DW_AT_external
$C$DW$10 .dwtag DW_TAG_subprogram, DW_AT_name("MDIO_phyRegWrite")
.dwattr $C$DW$10, DW_AT_TI_symbol_name("_MDIO_phyRegWrite")
.dwattr $C$DW$10, DW_AT_type(*$C$DW$T$20)
.dwattr $C$DW$10, DW_AT_declaration
.dwattr $C$DW$10, DW_AT_external
$C$DW$11 .dwtag DW_TAG_formal_parameter, DW_AT_type(*$C$DW$T$20)
$C$DW$12 .dwtag DW_TAG_formal_parameter, DW_AT_type(*$C$DW$T$20)
$C$DW$13 .dwtag DW_TAG_formal_parameter, DW_AT_type(*$C$DW$T$47)
.dwendtag $C$DW$10
_LinkStr: .usect ".far",20,8
$C$DW$14 .dwtag DW_TAG_variable, DW_AT_name("LinkStr")
.dwattr $C$DW$14, DW_AT_TI_symbol_name("_LinkStr")
.dwattr $C$DW$14, DW_AT_type(*$C$DW$T$64)
.dwattr $C$DW$14, DW_AT_location[DW_OP_addr _LinkStr]
_bMacAddr: .usect ".far",8,8
$C$DW$15 .dwtag DW_TAG_variable, DW_AT_name("bMacAddr")
.dwattr $C$DW$15, DW_AT_TI_symbol_name("_bMacAddr")
.dwattr $C$DW$15, DW_AT_type(*$C$DW$T$42)
.dwattr $C$DW$15, DW_AT_location[DW_OP_addr _bMacAddr]
; C:\CCStudio_v3.3\C6000\cgtools\bin\opt6x.exe C:\\DOCUME~1\\ADMINI~1\\LOCALS~1\\Temp\\002242 C:\\DOCUME~1\\ADMINI~1\\LOCALS~1\\Temp\\002244
.sect ".text"
.global _dm642_init
$C$DW$16 .dwtag DW_TAG_subprogram, DW_AT_name("dm642_init")
.dwattr $C$DW$16, DW_AT_low_pc(_dm642_init)
.dwattr $C$DW$16, DW_AT_high_pc(0x00)
.dwattr $C$DW$16, DW_AT_TI_symbol_name("_dm642_init")
.dwattr $C$DW$16, DW_AT_external
.dwattr $C$DW$16, DW_AT_TI_begin_file("dm642init.c")
.dwattr $C$DW$16, DW_AT_TI_begin_line(0x25)
.dwattr $C$DW$16, DW_AT_TI_begin_column(0x06)
.dwattr $C$DW$16, DW_AT_frame_base[DW_OP_breg31 8]
.dwattr $C$DW$16, DW_AT_TI_skeletal
.dwpsn file "dm642init.c",line 38,column 1,is_stmt,address _dm642_init
;******************************************************************************
;* FUNCTION NAME: dm642_init *
;* *
;* Regs Modified : A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,B0,B1,B2,B3,B4,B5,B6, *
;* B7,B8,B9,SP,A16,A17,A18,A19,A20,A21,A22,A23,A24, *
;* A25,A26,A27,A28,A29,A30,A31,B16,B17,B18,B19,B20, *
;* B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31 *
;* Regs Used : A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,B0,B1,B2,B3,B4,B5,B6, *
;* B7,B8,B9,SP,A16,A17,A18,A19,A20,A21,A22,A23,A24, *
;* A25,A26,A27,A28,A29,A30,A31,B16,B17,B18,B19,B20, *
;* B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31 *
;* Local Frame Size : 0 Args + 0 Auto + 4 Save = 4 byte *
;******************************************************************************
_dm642_init:
;** --------------------------------------------------------------------------*
MVKL .S1 0x1848200,A4
|| STW .D2T2 B3,*SP--(8) ; |38|
MVKH .S1 0x1848200,A4
LDW .D1T1 *A4,A5 ; |413|
MV .L1 A4,A3 ; |413|
NOP 3
OR .L1 1,A5,A5 ; |413|
STW .D1T1 A5,*A4 ; |413|
LDW .D1T1 *A3,A3 ; |414|
MV .L1 A4,A5 ; (P) <0,0>
NOP 3
AND .L1 1,A3,A0 ; |414|
[ A0] BNOP .S1 $C$L4,4 ; |414|
|| [!A0] LDW .D1T1 *A5,A3 ; |414| (P) <0,1> ^
|| [!A0] MVK .L2 0x1,B0
AND .L1 1,A3,A0 ; |414| (P) <0,6> ^
; BRANCHCC OCCURS {$C$L4} ; |414|
;*----------------------------------------------------------------------------*
;* SOFTWARE PIPELINE INFORMATION
;*
;* Loop source line : 414
;* Loop closing brace source line : 414
;* Known Minimum Trip Count : 1
;* Known Max Trip Count Factor : 1
;* Loop Carried Dependency Bound(^) : 7
;* Unpartitioned Resource Bound : 1
;* Partitioned Resource Bound(*) : 1
;* Resource Partition:
;* A-side B-side
;* .L units 0 0
;* .S units 0 1*
;* .D units 1* 0
;* .M units 0 0
;* .X cross paths 0 0
;* .T address paths 1* 0
;* Long read paths 0 0
;* Long write paths 0 0
;* Logical ops (.LS) 0 0 (.L or .S unit)
;* Addition ops (.LSD) 2 1 (.L or .S or .D unit)
;* Bound(.L .S .LS) 0 1*
;* Bound(.L .S .D .LS .LSD) 1* 1*
;*
;* Searching for software pipeline schedule at ...
;* ii = 7 Schedule found with 2 iterations in parallel
;*
;* Register Usage Table:
;* +-----------------------------------------------------------------+
;* |AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA|BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB|
;* |00000000001111111111222222222233|00000000001111111111222222222233|
;* |01234567890123456789012345678901|01234567890123456789012345678901|
;* |--------------------------------+--------------------------------|
;* 0: |* ** |* |
;* 1: | *** |* |
;* 2: | ** |* |
;* 3: | ** |* |
;* 4: | ** |* |
;* 5: | ** |* |
;* 6: | ** |* |
;* +-----------------------------------------------------------------+
;*
;* Done
;*
;* Loop is interruptible
;* Collapsed epilog stages : 1
;* Prolog not removed
;* Collapsed prolog stages : 0
;*
;* Minimum required memory pad : 0 bytes
;*
;* Minimum safe trip count : 1
;*----------------------------------------------------------------------------*
;* SETUP CODE
;*
;* MVK 0x1,B0
;* ZERO A3
;*
;* SINGLE SCHEDULED ITERATION
;*
;* $C$C65:
;* 0 MV .L1 A4,A5
;* 1 [ B0] LDW .D1T1 *A5,A3 ; |414| ^
;* 2 NOP 4
;* 6 AND .L1 1,A3,A0 ; |414| ^
;* 7 [ A0] ZERO .L2 B0 ; |414| ^
;* 8 [ B0] B .S2 $C$C65 ; |414|
;* 9 NOP 5
;* 14 ; BRANCHCC OCCURS {$C$C65} ; |414|
;*----------------------------------------------------------------------------*
$C$L1: ; PIPED LOOP PROLOG
;** --------------------------------------------------------------------------*
$C$L2: ; PIPED LOOP KERNEL
$C$DW$L$_dm642_init$3$B:
[ A0] ZERO .L2 B0 ; |414| <0,7> ^
|| MV .L1 A4,A5 ; <1,0>
[ B0] BNOP .S2 $C$L2,4 ; |414| <0,8>
|| [ B0] LDW .D1T1 *A5,A3 ; |414| <1,1> ^
AND .L1 1,A3,A0 ; |414| <1,6> ^
$C$DW$L$_dm642_init$3$E:
;** --------------------------------------------------------------------------*
$C$L3: ; PIPED LOOP EPILOG
;** --------------------------------------------------------------------------*
$C$L4:
ADD .L1 4,A4,A3
|| ADD .S1 4,A4,A4
LDW .D1T1 *A4,A5 ; |413|
NOP 4
OR .L1 1,A5,A5 ; |413|
STW .D1T1 A5,*A4 ; |413|
LDW .D1T1 *A3,A3 ; |414|
MV .L1 A4,A5 ; (P) <0,0>
NOP 3
AND .L1 1,A3,A0 ; |414|
[ A0] BNOP .S1 $C$L8,4 ; |414|
|| [!A0] LDW .D1T1 *A5,A3 ; |414| (P) <0,1> ^
|| [!A0] MVK .L2 0x1,B0
AND .L1 1,A3,A0 ; |414| (P) <0,6> ^
; BRANCHCC OCCURS {$C$L8} ; |414|
;*----------------------------------------------------------------------------*
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