📄 jpegmain.asm
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$C$RL1: ; CALL OCCURS {__CSL_init} ; |176|
MVKL .S2 _CACHE_clean,B5 ; |176|
MVKH .S2 _CACHE_clean,B5 ; |176|
CALL .S2 B5 ; |176|
ADDKPC .S2 $C$RL2,B3,3 ; |176|
ZERO .L2 B4 ; |176|
|| ZERO .L1 A6 ; |176|
|| MVK .S1 0x1,A4 ; |176|
$C$RL2: ; CALL OCCURS {_CACHE_clean} ; |176|
MVKL .S2 _CACHE_setL2Mode,B4 ; |21|
MVKH .S2 _CACHE_setL2Mode,B4 ; |21|
CALL .S2 B4 ; |21|
ADDKPC .S2 $C$RL3,B3,3 ; |21|
MVK .L1 0x3,A4 ; |21|
$C$RL3: ; CALL OCCURS {_CACHE_setL2Mode} ; |21|
;** --------------------------------------------------------------------------*
MVKL .S1 0x1848200,A4
MVKH .S1 0x1848200,A4
LDW .D1T1 *A4,A5 ; |413|
MV .L1 A4,A3 ; |413|
NOP 3
OR .L1 1,A5,A5 ; |413|
STW .D1T1 A5,*A4 ; |413|
LDW .D1T1 *A3,A3 ; |414|
MV .L1 A4,A5 ; (P) <0,0>
NOP 3
AND .L1 1,A3,A0 ; |414|
[ A0] BNOP .S1 $C$L4,4 ; |414|
|| [!A0] LDW .D1T1 *A5,A3 ; |414| (P) <0,1> ^
|| [!A0] MVK .L2 0x1,B0
AND .L1 1,A3,A0 ; |414| (P) <0,6> ^
; BRANCHCC OCCURS {$C$L4} ; |414|
;*----------------------------------------------------------------------------*
;* SOFTWARE PIPELINE INFORMATION
;*
;* Loop source line : 414
;* Loop closing brace source line : 414
;* Known Minimum Trip Count : 1
;* Known Max Trip Count Factor : 1
;* Loop Carried Dependency Bound(^) : 7
;* Unpartitioned Resource Bound : 1
;* Partitioned Resource Bound(*) : 1
;* Resource Partition:
;* A-side B-side
;* .L units 0 0
;* .S units 0 1*
;* .D units 1* 0
;* .M units 0 0
;* .X cross paths 0 0
;* .T address paths 1* 0
;* Long read paths 0 0
;* Long write paths 0 0
;* Logical ops (.LS) 0 0 (.L or .S unit)
;* Addition ops (.LSD) 2 1 (.L or .S or .D unit)
;* Bound(.L .S .LS) 0 1*
;* Bound(.L .S .D .LS .LSD) 1* 1*
;*
;* Searching for software pipeline schedule at ...
;* ii = 7 Schedule found with 2 iterations in parallel
;*
;* Register Usage Table:
;* +-----------------------------------------------------------------+
;* |AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA|BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB|
;* |00000000001111111111222222222233|00000000001111111111222222222233|
;* |01234567890123456789012345678901|01234567890123456789012345678901|
;* |--------------------------------+--------------------------------|
;* 0: |* ** |* |
;* 1: | *** |* |
;* 2: | ** |* |
;* 3: | ** |* |
;* 4: | ** |* |
;* 5: | ** |* |
;* 6: | ** |* |
;* +-----------------------------------------------------------------+
;*
;* Done
;*
;* Loop is interruptible
;* Collapsed epilog stages : 1
;* Prolog not removed
;* Collapsed prolog stages : 0
;*
;* Minimum required memory pad : 0 bytes
;*
;* Minimum safe trip count : 1
;*----------------------------------------------------------------------------*
;* SETUP CODE
;*
;* MVK 0x1,B0
;* ZERO A3
;*
;* SINGLE SCHEDULED ITERATION
;*
;* $C$C67:
;* 0 MV .L1 A4,A5
;* 1 [ B0] LDW .D1T1 *A5,A3 ; |414| ^
;* 2 NOP 4
;* 6 AND .L1 1,A3,A0 ; |414| ^
;* 7 [ A0] ZERO .L2 B0 ; |414| ^
;* 8 [ B0] B .S2 $C$C67 ; |414|
;* 9 NOP 5
;* 14 ; BRANCHCC OCCURS {$C$C67} ; |414|
;*----------------------------------------------------------------------------*
$C$L1: ; PIPED LOOP PROLOG
;** --------------------------------------------------------------------------*
$C$L2: ; PIPED LOOP KERNEL
$C$DW$L$_main$5$B:
[ A0] ZERO .L2 B0 ; |414| <0,7> ^
|| MV .L1 A4,A5 ; <1,0>
[ B0] BNOP .S2 $C$L2,4 ; |414| <0,8>
|| [ B0] LDW .D1T1 *A5,A3 ; |414| <1,1> ^
AND .L1 1,A3,A0 ; |414| <1,6> ^
$C$DW$L$_main$5$E:
;** --------------------------------------------------------------------------*
$C$L3: ; PIPED LOOP EPILOG
;** --------------------------------------------------------------------------*
$C$L4:
ADD .L1 4,A4,A3
|| ADD .S1 4,A4,A4
LDW .D1T1 *A4,A5 ; |413|
NOP 4
OR .L1 1,A5,A5 ; |413|
STW .D1T1 A5,*A4 ; |413|
LDW .D1T1 *A3,A3 ; |414|
MV .L1 A4,A5 ; (P) <0,0>
NOP 3
AND .L1 1,A3,A0 ; |414|
[ A0] BNOP .S1 $C$L8,4 ; |414|
|| [!A0] LDW .D1T1 *A5,A3 ; |414| (P) <0,1> ^
|| [!A0] MVK .L2 0x1,B0
AND .L1 1,A3,A0 ; |414| (P) <0,6> ^
; BRANCHCC OCCURS {$C$L8} ; |414|
;*----------------------------------------------------------------------------*
;* SOFTWARE PIPELINE INFORMATION
;*
;* Loop source line : 414
;* Loop closing brace source line : 414
;* Known Minimum Trip Count : 1
;* Known Max Trip Count Factor : 1
;* Loop Carried Dependency Bound(^) : 7
;* Unpartitioned Resource Bound : 1
;* Partitioned Resource Bound(*) : 1
;* Resource Partition:
;* A-side B-side
;* .L units 0 0
;* .S units 0 1*
;* .D units 1* 0
;* .M units 0 0
;* .X cross paths 0 0
;* .T address paths 1* 0
;* Long read paths 0 0
;* Long write paths 0 0
;* Logical ops (.LS) 0 0 (.L or .S unit)
;* Addition ops (.LSD) 2 1 (.L or .S or .D unit)
;* Bound(.L .S .LS) 0 1*
;* Bound(.L .S .D .LS .LSD) 1* 1*
;*
;* Searching for software pipeline schedule at ...
;* ii = 7 Schedule found with 2 iterations in parallel
;*
;* Register Usage Table:
;* +-----------------------------------------------------------------+
;* |AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA|BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB|
;* |00000000001111111111222222222233|00000000001111111111222222222233|
;* |01234567890123456789012345678901|01234567890123456789012345678901|
;* |--------------------------------+--------------------------------|
;* 0: |* ** |* |
;* 1: | *** |* |
;* 2: | ** |* |
;* 3: | ** |* |
;* 4: | ** |* |
;* 5: | ** |* |
;* 6: | ** |* |
;* +-----------------------------------------------------------------+
;*
;* Done
;*
;* Loop is interruptible
;* Collapsed epilog stages : 1
;* Prolog not removed
;* Collapsed prolog stages : 0
;*
;* Minimum required memory pad : 0 bytes
;*
;* Minimum safe trip count : 1
;*----------------------------------------------------------------------------*
;* SETUP CODE
;*
;* MVK 0x1,B0
;* ZERO A3
;*
;* SINGLE SCHEDULED ITERATION
;*
;* $C$C32:
;* 0 MV .L1 A4,A5
;* 1 [ B0] LDW .D1T1 *A5,A3 ; |414| ^
;* 2 NOP 4
;* 6 AND .L1 1,A3,A0 ; |414| ^
;* 7 [ A0] ZERO .L2 B0 ; |414| ^
;* 8 [ B0] B .S2 $C$C32 ; |414|
;* 9 NOP 5
;* 14 ; BRANCHCC OCCURS {$C$C32} ; |414|
;*----------------------------------------------------------------------------*
$C$L5: ; PIPED LOOP PROLOG
;** --------------------------------------------------------------------------*
$C$L6: ; PIPED LOOP KERNEL
$C$DW$L$_main$9$B:
[ A0] ZERO .L2 B0 ; |414| <0,7> ^
|| MV .L1 A4,A5 ; <1,0>
[ B0] BNOP .S2 $C$L6,4 ; |414| <0,8>
|| [ B0] LDW .D1T1 *A5,A3 ; |414| <1,1> ^
AND .L1 1,A3,A0 ; |414| <1,6> ^
$C$DW$L$_main$9$E:
;** --------------------------------------------------------------------------*
$C$L7: ; PIPED LOOP EPILOG
;** --------------------------------------------------------------------------*
$C$L8:
MVKL .S1 _DAT_open,A3 ; |25|
MVKH .S1 _DAT_open,A3 ; |25|
ZERO .L1 A4 ; |25|
CALL .S2X A3 ; |25|
MVK .L2 0x3,B4 ; |25|
MVK .L1 0x1,A6 ; |25|
ADDKPC .S2 $C$RL4,B3,2 ; |25|
$C$RL4: ; CALL OCCURS {_DAT_open} ; |25|
;** --------------------------------------------------------------------------*
MVKL .S2 0x184200c,B4
MVKH .S2 0x184200c,B4
LDW .D2T2 *B4,B5 ; |428|
ADD .L2 -8,B4,B31
ZERO .L2 B30 ; |424|
MVKH .S2 0x1840000,B30 ; |424|
NOP 1
OR .L2 7,B5,B5 ; |428|
STW .D2T2 B5,*B4 ; |428|
LDW .D2T2 *B31,B5 ; |428|
ZERO .L2 B4 ; |424|
MVKH .S2 0x1840000,B4 ; |424|
NOP 2
OR .L1X 7,B5,A3 ; |428|
STW .D2T1 A3,*B31 ; |428|
|| MVKL .S1 _ACPY2_6X1X_init,A3 ; |424|
LDW .D2T2 *B30,B5 ; |424|
|| MVKH .S1 _ACPY2_6X1X_init,A3 ; |424|
NOP 1
CALL .S2X A3 ; |424|
ADDKPC .S2 $C$RL5,B3,1 ; |424|
EXTU .S2 B5,3,3,B5 ; |424|
SET .S2 B5,29,29,B5 ; |424|
STW .D2T2 B5,*B4 ; |424|
$C$RL5: ; CALL OCCURS {_ACPY2_6X1X_init} ; |424|
MVKL .S1 _DMAN_init,A3 ; |33|
MVKH .S1 _DMAN_init,A3 ; |33|
NOP 1
CALL .S2X A3 ; |33|
ADDKPC .S2 $C$RL6,B3,4 ; |33|
$C$RL6: ; CALL OCCURS {_DMAN_init} ; |33|
MVKL .S2 _DMAN_setup,B4 ; |34|
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